Re: FPI

[larry@lablues.UUCP (Lawrance A. Schneider)]

David Epson scribed the following bit of his almost infinite knowledge
with my questions interspersed:

|If you've read the IIgs Hardware Reference, you've read all the
|documentation that there is on the FPI (at least, all that I'm aware 
of).

I have; other than saying what it does, ??????

|The refresh mechanism is pretty simple.  All it needs is a 7 (?) bit
|counter.  Every few microseconds, the FPI performs a RAS-only access
|to all RAM chips, addressing the row currently selected by the 
counter.
|                  ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|If the micro is trying to address the fast RAM at the same time, the
|FPI causes it to wait.

Thus, my question about timing; how does it get itself back in sink
without passing at least one cycle. 

|                          The micro can access ROM and slow RAM 
without
|interference from the memory refresh.
|
|If the processor is accessing fast RAM exclusively, the net effect of
|the cycles stolen for refresh is that the IIgs runs at about 2.5 MHz
|instead of its maximum 2.8 MHz.

Thus, if the micro is not accessing the same row, there should be no
need for any pause on that particular cycle.  Is there a connection
between my two questions?  What am I missing?

|I'm not sure of the details about how many bits are required in the
|counter (it may be 10, to allow for 1 megabit RAMs), or what
|differences there are between refreshing the motherboard and RAM
|expansion slot, or what the period is between refresh cycles 
(estimate:
|3.3 microseconds).

larry@lablues.UUCP
FidoNet:  1:132/300 Larry Schneider

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