Re: TWGS vs. ZipChip

[toddpw@cco.caltech.edu (Todd P. Whitesel)]

foegelle@ccwf.cc.utexas.edu (Michael Foegelle) writes:

>I would be interested to see a GS tested for class B with a Zip running at 
>about 15 MHz or so..  The fact that the low power Zips and RamFASTs flake
>out sometimes could very well be due to them failing class A certification 

The GS case is one large faraday cage, so I'm not sure how much this really
matters. In the case of the Zip there is very strong evidence that the original
two-layer board design simply could not filter out noise in the power rails --
which low power CMOS is very sensitive to. My best info on the RAMfast so far
is that the low power drivers simply can't compete with noise on the data bus
generated by some peripherals and by the //e motherboard.

Your point about 15 mhz is a good one, though; I wouldn't be surprised if the
old Zip design simply doesn't run once you get much higher than that. Hopefully
the new four-layer board will be sufficiently quiet. Drew says his RAMfast D
board has Zero noise on the power rails, it's the busses to the rest of the
system that are the problem.

Todd Whitesel
toddpw @ cco.caltech.edu