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Re: Transwarp IIe revisited

mdj wrote:

On Dec 9, 11:43 am, "Michael J. Mahon" <mjma...@aol.com> wrote:


mdj wrote:


On Dec 8, 11:50 pm, Linards Ticmanis <ticma...@gmx.de> wrote:



David Wilson wrote:



On Dec 8, 7:51 pm, mdj <mdj....@gmail.com> wrote:



FWIW, my card has 80ns RAM on it. I imagine someone has swapped the
RAM at some earlier point, 150 is way to slow



I just took a look at mine and it has 8x HM50256-15 NMOS DRAM chips
(week 50 of 1985).



Hmmm... I have HM50256P-15 from WK13/86. Then speed is maybe not the
issue after all.



Unless one or more of them is faulty...



I didn't do the math, but I would have thought 150ns was marginal at
3.6Mhz considering the Apple II refresh scheme.


The Apple II "interleaved access" scheme will not apply to
DRAM on the Transwarp card.  It will have its own, more conventional
refresh method.



I had suspected that it would, since it still uses its own CPU in
'slow' mode so would need to mimic the timing of the Apple II...

But then I suppose it could have different refresh schemes for
different speeds, but that seems unlikely...


Since it doesn't have to refresh the video display from its on-board
memory, it has considerable flexibility in how it handles refresh.

All it has to do to interface to the bus is wait for a bus cycle.
To run "slow mode" code, it just waits for the bus (1MHz) clock.

I'd guess that it latches write data to be written on the next bus
cycle when it's in "fast" mode, so it doesn't have to wait until a
second byte needs to be written within a microsecond, but I don't
have a Transwarp to find out.

I wonder if there's a Transwarp patent that covers its design...?

-michael

NadaPong: Network game demo for Apple II computers!
Home page:  http://members.aol.com/MJMahon/

"The wastebasket is our most important design
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