On Feb 27, 7:31 am, demp...@actrix.gen.nz (David Empson) wrote:
The horizontal line is the same width in SHR and other video modes,
implying the same time (about 40 microseconds) for the active portion of
the row, so it must have a higher frequency dot clock in order to fit
320 or 640 pixels in the same space as 280 or 560 for other modes.
David, have you actually verified that they are the same width with
your eyeballs and a ruler? Just curious if this is an established
fact now.
If I remember right, the IIgs has a master clock frequency of 28.63636
MHz. Deriving 8.18181 from that is reasonably OK: a divisor of 3.5, i.e.
7 half cycles. It would be harder to derive 16.36363 MHz, which would
require a divisor of 1.75. DPLL, perhaps?
Looking at the IIgs schematic, the VGC has both a 14M and 28M clock
input. 28M is generated by a dedicated oscillator nearby. The only
other signals of interest are coming from a chip named SERCLK which
itself is driven by a 32.768khz crystal, and is powered at times by
the Lithium Battery. I suppose this is a clock chip.
This clock chip is for some reason connected to several of the VGC
inputs -- CLKCS, DATA, CLK, 1SEC, and 3.5DIK. Not sure what that's
mean, but David mentioned 3.5 divisor above. A bell has rung.