Re: IIgs video modes...

[dempson@actrix.gen.nz (David Empson)]

jsnospam@cimmeri.com <js@cimmeri.com> wrote:

> On Feb 27, 7:31 am, demp...@actrix.gen.nz (David Empson) wrote:
> > The horizontal line is the same width in SHR and other video modes,
> > implying the same time (about 40 microseconds) for the active portion of
> > the row, so it must have a higher frequency dot clock in order to fit
> > 320 or 640 pixels in the same space as 280 or 560 for other modes.
> 
> David, have you actually verified that they are the same width with
> your eyeballs and a ruler?  Just curious if this is an established
> fact now.

Yes, I just checked.

If anything, SHR mode is a fraction narrower (about 2 mm) than text
mode, and the entire screen offset to the left about 2 mm. These are
probably artifacts of my old greenscreen composite monitor, depending on
how many pixels are illuminated.

> > If I remember right, the IIgs has a master clock frequency of 28.63636
> > MHz. Deriving 8.18181 from that is reasonably OK: a divisor of 3.5, i.e.
> > 7 half cycles. It would be harder to derive 16.36363 MHz, which would
> > require a divisor of 1.75. DPLL, perhaps?
> 
> Looking at the IIgs schematic, the VGC has both a 14M and 28M clock
> input.

14M is probably an output for the rest of the computer (particularly the
Mega II and FPI/CYA), derived from the 28M input.

> 28M is generated by a dedicated oscillator nearby.   The only
> other signals of interest are coming from a chip named SERCLK which
> itself is driven by a 32.768khz crystal, and is powered at times by
> the Lithium Battery.  I suppose this is a clock chip.

That's the parameter RAM and real time clock. Not directly related to
video. The VGC provides the memory mapped I/O to access it.

> This clock chip is for some reason connected to several of the VGC
> inputs -- CLKCS, DATA, CLK, 1SEC, and 3.5DIK.   Not sure what that's
> mean, but David mentioned 3.5 divisor above.  A bell has rung.

None of that matters. CLKCS, DATA and CLK are the serial data access
signals used to read or write the RTC/PRAM chip. 1SEC is an input to the
VGC which generates an interrupt every second. 3.5DIK is a 3.5 disk
enable line which goes out the drive port, but I'm not sure why it is in
that neighbourhood.

The video timing must be kept in sync with 28M, so it wouldn't make
sense to have another 16M clock input just for SHR mode. All the timings
for SHR mode must be derived from 28M.

If they haven't used a DPLL to derive a higher frequency, perhaps 640
mode uses an asymmetrical clock: 1.75 cycles of 28M could be implemented
as 3.5 half-cycles, alternating between 3 and 4 half-cycle counts.

This seems a little unlikely: it would result in odd and even columns of
pixels in 640 mode having different widths, but they might be able to
gloss over this due to the coarse horizontal resolution of the monitor,
together with dithering effects.

-- 
David Empson
dempson@actrix.gen.nz