Re: 6502 emulation update

[Charlie Springer <RAM@regnirps.com>]

On Wed, 3 Jan 2007 00:10:39 -0800, Charlie Springer wrote
(in article <0001HW.C1C0A4FF0001A5D8F02845B0@news.nw.centurytel.net>):

> Turns out the Xilinx CPLD is arranged as two really big PALs/GALs. U used a 
> lot of 16V8's and such and these are like a pair of 54V18 GAL devices.

That is a possible 36 decodes. Is that going to be enough to cover the whole 
//e memory map? I need a good simple map since I sold all my good Apple II 
hardware books. Need to handle the various ROM/slot spaces and anyplace else 
I/O is mapped (soft switches, etc.)

I bet FPGA Apple (or whatever the name is) must have complete descriptions.

-- Charlie Springer