Re: Supercard

["Keith" <chen.evans@gmail.com>]

Michael J. Mahon wrote:
> Keith wrote:
> > Michael J. Mahon wrote:
> >
> >>Keith wrote:
> >>
> >>>>It's so easy to do, you might as well, assuming you've got room for it
> >>>>in the FGPA (two processor cores is likely to eat a lot of room)
> >>>>
> >>>>Matt
> >>>
> >>>
> >>>Based on my experience with the Xilinx Spartan XC3S1000 (Digilent
> >>>Spartan-3 Board) I would guess that you could just about squeeze an
> >>>entire AppleCrate onto one. And the communications channel could be
> >>>much faster than that used on an AppleCrate. Don't know if anyone would
> >>>be interested in that or not. You could probably clock them faster than
> >>>an AppleCrate too, but maybe not much faster since you would probably
> >>>be time domain multiplexing the SRAM to provide enough memory to the
> >>>CPU cores.
> >>
> >>Cool!  ;-)
> >>
> >>Of course, with both on-chip and shared memory communication possible,
> >>the entire networking premise of AppleCrate would be unneeded.  A much
> >>closer coupling should be supported--closer to SMP.
> >>
> >>It's fun to think about hi-tech approaches to lo-tech problems!  ;-)
> >>
> >>-michael
> >>
> >>Parallel computing for 8-bit Apple II's!
> >>Home page:  http://members.aol.com/MJMahon/
> >>
> >>"The wastebasket is our most important design
> >>tool--and it is seriously underused."
> >
> >
> > How much of an Apple II would one need to emulate in order to get the
> > client-side of AppleCrate working? Assume that it would use the same
> > networking as your box is using, and not some new invention. It would
> > seem that you could leave out a lot of the logic that makes an Apple II
> > and Apple II. Is this correct? If it's not too bad I might try to do it
> > for fun.
>
> The only thing required to participate in a NadaNet network (which is
> what AppleCrate machines do) is the ability to bit-bang the serial
> network line at 94-95 Apple cycles per byte (8 cycles per bit) and
> sense them if receiving (while maintaining phase lock within 3 cycles).
>
> The rigidity of the timing requirements makes it hard to do in any
> environment in which interrupts can cause jitter of more than a
> microsecond per byte, like PCs and Macs, unless interrupts can be
> disabled for the duration of a packet, which could be nearly 25
> milliseconds (which is also problematic for PCs and Macs).
>
> There should be no problem at all meeting these requirements using
> a microcontroller or hardware.  Of course, the protocols for actually
> using the network for something would also need to be implemented,
> and they currently exist only as 6502 code, optionally invoked by
> ampersand routines in Applesoft.
>
> -michael

I meant for example what portions of the Apple II ROMs would be needed,
what control and status registers would need to be implemented. For
example you wouldn't really need any graphics capability would you?
(Maybe useful for debugging.) I guess that you need to provide whatever
is necessary to keep Applesoft from hanging. If it's polling some
status register then the hardware better do something reasonable.

Maybe this is a really detailed question and not something that you
would want to answer in great detail. But the idea is to strip out
everything nonessential in order to speed development, and to minimize
gate count.

Regards,
Keith