Re: Read full 8-bit character from serial port?

[dempson@actrix.gen.nz (David Empson)]

Jorge Chamorro Bieling <bieling@terra.es> wrote:

> David Empson <dempson@actrix.gen.nz> wrote:
> 
> > 
> > The standard Z8530 SCC has a 3 byte rx buffer. The ESCC (Z85230) has an
> > 8 byte buffer.
> >
> > Assuming 9600 bps with 8-n-1 data, if you aren't using interrupts, you
> > will have to poll the SCC at least once every 3 milliseconds (on
> > average) to avoid losing characters, and if you are polling it less
> > often than once every millisecond, you may have to receive several
> > characters in a loop to avoid running out of buffer space.
> 
> More or less. Keep in mind that :
> 
> 1.- There can be 3 rx chars standing in the 3 bytes deep rx buffer and
> at the same time a 4th rx char being assembled (received) into the
> receiver, and you won't get an overrun.

Agreed. You have most of an extra character time before losing the first
character.

> 2.- Once a 4th rx char has been completely assembled (received) into the
> receiver, you won't get an overrun either : the receiver can be thought
> off as a 4th buffer byte.
> 
> 3.- In fact it's not until the *5th* rx char start bit appears at the
> SCC RxD pin that an overrun will happen.

I doubt that is correct.

I don't remember whether I've tested the SCC to this level of detail,
but my experience with a wide range of serial hardware (programming them
is a major part of my job) is that when I've actually encountered this
situation and had borderline timing issues, the standard behaviour is
that as soon as the stop bit is detected (half way through the bit
cell), the shift register will be transferred into the buffer register
(or FIFO). If the buffer register is full at this point, an overrun
error will occur and the byte in the shift register is lost.

Assuming this behaviour also applies to the SCC, you get 3.95 character
times before losing a byte (also assuming no gaps between bytes).

Some serial interface designers might have "played nice" and given you
until the next start bit is detected, but doing so would require an
extra state or flag bit, and wasting silicon to allow for a borderline
programming error (and 0.1 of a character time) isn't something that
chip designers are likely to do.
-- 
David Empson
dempson@actrix.gen.nz