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Re: Zip Chip programming info / disk image?
RedskullDC wrote:
<snip>
Thanks for the pointers, I found the zip8000 disk on Asimov ok.
the tech.details file is sufficiently detailed to explain the inner
workings.
Was the schematic diagram in the recently posted zip patent docs
accurate? I noticed it shows a 2716 eprom, which makes me thing this was
for an earlier (later?) expansion card style design of the zip chip?
The patent describes the McT SpeedDemon card.
One thing that doesn't appear to be covered is whether it co-exists
with DMA capable devices?
Does it actually work with DMA devices? If so, I assume it would
invalidate all entries in the tag/cache memories after it sees a DMA
transfer (phase 0 clock input to the zip-chip being held low temporarily?)
This heuristic might work, but without access to the slot DMA signal
it's more difficult.
I don't have any DMA cards, so this is no big deal to me, but I guess it
could be for those with DMA scsi cards etc. who may like to build one
of these.
It would be reasonably easy to replicate the register set that the
zip-chip uses, but the whole tag ram scheme seems somewhat limiting.
It's just a classic direct-mapped 8KB cache. So three bits of the tag
specify the high address bits (the "8K page number") and the remaining
5 bits track a RamWorks-style AUX RAM card bank, providing cache support
for up to 2MB.
Ideally, I would like to never write to Apple2 main memory at all, only
to addresses within $C000-$CFFF, and even then some of those could
be intercepted (such as a PS/2 keyboard driver, for the PS/2 keyboard
interface hanging off the FPGA board.)
Then DMA support is both more important and more complex.
The 50ms slow-down timer seems like a good idea to maintain compatibility
with normal apple peripheral cards: disk2 , SSC etc.
Applesoft/Integer/Language Card/Main Mem can all be in a 12ns
SRAM hanging off the FPGA.
Initially, writes to the text/gr/hgr pages would have to go to the main
board,
until VGA drivers are working, then they can go off to the SRAMS
aswell.
Since you are significantly accelerating the machine, support for
at least 1MB of "AUX RAM" would also be a good idea.
The ZIP-Chip seems best documented, so it is probably easiest to
replicate to allow existing software to function as-is.
I agree about the documentation, but very little software actually
"uses" the Zip Chip, or any other accelerator, directly.
-michael
Music synthesis for 8-bit Apple II's!
Home page: http://members.aol.com/MJMahon/
"The wastebasket is our most important design
tool--and it is seriously underused."