Re: 14MHz Osc Chip Question

[mjmahon@aol.com (Michael J. Mahon)]

Roy wrote:

>Michael J. Mahon wrote:
>> Bryan Parkoff asked:
>> 
>> 
>>>   I seem to understand, but you did not answer my question.  What do clock
>>>pulse and cycle mean?
>>>
>>>   I understand that Hertz is the same as Cycle.  Hertz only executes each
>>>one second.  It is what the dictionary said, but it is probably wrong.  If
>>>it is possible, Hertz is truly to be executed each one millisecond.  It
>>>should be .001 cycle each one second.  It would be 1,000,000 cycles per
>>>second or 1MHz.  Minimum 142,857 instructions are executed each one second.
>>>Maximum 500,000 instructions are executed each one second.  Average 222,222
>>>instructions between 142,857 and 500,000 instructions are executed each one
>>>second.  Does it make sense?
>> 
>> 
>> One Hertz is one cycle per second.  "Cycle" is a full period of a waveform,
>> with no information about frequency at all.  "Cycles per second" is a
>measure
>> of frequency, also known as "Hertz".
>> 
>> The clock waveform of an Apple II (like most digital electronics) is
>> approximately a square wave, at a frequency of approximately
>> 1MHz, or 1 million cycles per second.
>> 
>> Your calculations of the minimum and maximum instruction rates for
>> a 6502 running at 1MHz are correct (for 7-cycle and 2-cycle instructions,
>> respectively.  The average rate is, however, not easily known, since it
>> depends on the dynamic mix of instructions executed, and that varies
>> quite a lot from moment to moment and program to program.
>
>The creators of the 65c02 and 65816 claim 500,000 instructions per 
>second at 1 mhz.
>
>I assume that's 8 bit instructions on both chips. Given the need to 
>fetch twice, I would guess a drop off for 16 bit instructions. Am I 
>wrong? I'm guessing on the basis of the 8086 being (allegedly) almost 
>twice as fast as the 8088.

The creators' claims are the "absolute maximum" speed of the
processor, when doing only the fastest, 2-cycle, instructions.

The 6502 has 1-, 2-, and 3-byte instructions, and some include
indexing and/or indirection.  Some instructions are read-modify-
write instructions, like INC and DEC.

Since no memory reference instruction can be completed in less
than 3 cycles, we must assume that no interesting program could
ever run at the 500,000 instruction-per-second speed.

A rule of thumb for 6502 instruction times is obtained simply by
counting the memory cycles required (of course, this is a lower
bound on the number of cycles the instruction may require, but
the 6502 is quite efficient, and frequently achieves the lower
bound).

So, for example, a LDA from an absolute (2-byte) address is a
3-byte instruction, requiring 3 cycles to fetch, and one cycle to
read the value at the memory address, for a total of 4 cycles.

An LDX Immediate is a 2-byte instruction, requiring 2 cycles
to fetch, and the execution does not require any additional
memory cycles, so it is overlapped with the opcode fetch of
the next instruction.  Result:  LDX Immediate executes in
2 cycles.

Relative Branches are 2-byte instructions, so 2 cycles are
required to fetch the Branch instruction.  If the Branch is
not taken, then no additional time is required, but if it is
taken, then the fetch pipeline must be re-directed to the
out-of-line instruction, requiring an additional execution
cycle (actually, an additional fetch cycle for the Branch
target, but it is a direct consequence of the taken Branch.

You get the idea.

I am not familiar with the pipeline of the 65816, so I will
not comment on its timing, but you can be sure that the
number of memory references will play a determining
role.

-michael

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