Re: Apple IIe Tech Note #5 /INH Line

[a2retro <a2retrosystems@gmail.com>]

On Sep 20, 2:44 pm, aiiad...@gmail.com wrote:
> On Thursday, September 20, 2012 8:50:52 AM UTC-7, a2retro wrote:
> > Hi I was reviewing the /INH technote for the IIe and I was confused
>
> > about the operation of the sample circuit at the end of the tech note.
>
> > 1) The 2159 ram chip (which I can find no trace of on Google) shows an
>
> > active high for the write enable - should it not be active low like
>
> > the output enable?
>
> seperate write and output enables..  Active HI/LO to match
>
> H/L
> ---
> R/W
>
> (R=High, W=LOW)
>
> without other chips to invert signals? ?   ?   ?    ?     ?
>
> ???
>
>
>
> > 2) READDIS actually disables both reading and writing to the RAM?
>
> Looks like READDIS disables READs of peripheral card RAM, and forces READs to MOTHERBOARD:
>
> The circuit in Figure 3 can be used to replace the code in the monitor ROM, from location $FC00 to $FFFF, with custom code. Anytime the address space between $FC00-$FFFF is accessed, the /INH line is pulled low, the motherboard memory is disabled, and the circuit's 1K RAM is enabled instead.
>
> **************
> Part of this feature can be disabled and the motherboard memory can be read by keeping the switch connected to +5 volts (READDIS).
> **************
>
> Whenever the system writes to any location in the address space $FC00-$FFFF, the circuit will disable any RAM on the motherboard and instead write into the 1K RAM.
>
> > 3) If READEN is active I follow how a write from the A2 R/W signal
> > activates the INHIBIT but I don't follow how a READ enables it?
>
> READEN (READ PERIPHERAL CARD ENABLE) is active LOW...
>
> R/W  (Write= active LOW)
>
> Read HIGH through NAND (7400) used as inverter = LOW, 2159 OutputEnable is LOW, so 2159 is active to output its contents (A0-A9 attached to the address bus, D0-7 to data bus)
>
> Just looking at the circuit, not understanding your question?
>
> Inhibit is activated by :
>
>                 ________
>                |        |
>         A15 ---|        |
>                | Select |
>         A14 ---| Decode |
>                | Logic  |             _______
>         __/\/--|        |            |       |
>                |        |------------|D  7  Q|--- INH* J[1-7]32
>         A0  ---|        |  PULLINH*  |   4   |
>                |________|            |   L   |
>                                      |   S   |
>                 |\                   |   3   |
>         Q3  ----| >o-----------------|>  7   |
>                 |/                   |_  9   |
>         0o  -------------------------|G      |
>                                      |_______|
>
>             Figure 2 - Circuit Implementing /INH Function

Hi Rich you pasted the circuit in figure 2 - my question is about
figure 3


The R/W line feeds into an NAND gate along with the output from READEN/
READDIS/.

In the case of a WRITE to the RAM if READEN is low and R/W is low then
the output of the NAND gate will be high and (provided the out inputs
to the 379 are high) then INHIBIT will be pulled low thus activating
it.
In the case of a READ to the RAM if READEN is low and R/W is high then
the output of the NAND gate will be low so how does INHIBIT get
activated?

Glenn