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Re: Apple IIe Tech Note #5 /INH Line
On Thursday, September 20, 2012 12:21:20 PM UTC-7, a2retro wrote:
> On Sep 20, 2:44 pm, aiiad...@gmail.com wrote:
>
> > On Thursday, September 20, 2012 8:50:52 AM UTC-7, a2retro wrote:
>
> > > Hi I was reviewing the /INH technote for the IIe and I was confused
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> >
>
> > > about the operation of the sample circuit at the end of the tech note.
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> >
>
> > > 1) The 2159 ram chip (which I can find no trace of on Google) shows an
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> >
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> > > active high for the write enable - should it not be active low like
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> >
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> > > the output enable?
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> >
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> > seperate write and output enables.. Active HI/LO to match
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> >
>
> > H/L
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> > ---
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> > R/W
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> >
>
> > (R=High, W=LOW)
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> >
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> > without other chips to invert signals? ? ? ? ? ?
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> >
>
> > ???
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> >
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> >
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> >
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> > > 2) READDIS actually disables both reading and writing to the RAM?
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> >
>
> > Looks like READDIS disables READs of peripheral card RAM, and forces READs to MOTHERBOARD:
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> >
>
> > The circuit in Figure 3 can be used to replace the code in the monitor ROM, from location $FC00 to $FFFF, with custom code. Anytime the address space between $FC00-$FFFF is accessed, the /INH line is pulled low, the motherboard memory is disabled, and the circuit's 1K RAM is enabled instead.
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> >
>
> > **************
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> > Part of this feature can be disabled and the motherboard memory can be read by keeping the switch connected to +5 volts (READDIS).
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> > **************
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> >
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> > Whenever the system writes to any location in the address space $FC00-$FFFF, the circuit will disable any RAM on the motherboard and instead write into the 1K RAM.
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> >
>
> > > 3) If READEN is active I follow how a write from the A2 R/W signal
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> > > activates the INHIBIT but I don't follow how a READ enables it?
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> >
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> > READEN (READ PERIPHERAL CARD ENABLE) is active LOW...
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> >
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> > R/W (Write= active LOW)
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> >
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> > Read HIGH through NAND (7400) used as inverter = LOW, 2159 OutputEnable is LOW, so 2159 is active to output its contents (A0-A9 attached to the address bus, D0-7 to data bus)
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> >
>
> > Just looking at the circuit, not understanding your question?
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> >
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> > Inhibit is activated by :
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> >
>
> > ________
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> > | |
>
> > A15 ---| |
>
> > | Select |
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> > A14 ---| Decode |
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> > | Logic | _______
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> > __/\/--| | | |
>
> > | |------------|D 7 Q|--- INH* J[1-7]32
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> > A0 ---| | PULLINH* | 4 |
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> > |________| | L |
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> > | S |
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> > |\ | 3 |
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> > Q3 ----| >o-----------------|> 7 |
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> > |/ |_ 9 |
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> > 0o -------------------------|G |
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> > |_______|
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> >
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> > Figure 2 - Circuit Implementing /INH Function
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>
>
> Hi Rich you pasted the circuit in figure 2 - my question is about
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> figure 3
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> The R/W line feeds into an NAND gate along with the output from READEN/
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> READDIS/.
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> In the case of a WRITE to the RAM if READEN is low and R/W is low then
>
> the output of the NAND gate will be high and (provided the out inputs
>
> to the 379 are high) then INHIBIT will be pulled low thus activating
>
> it.
>
> In the case of a READ to the RAM if READEN is low and R/W is high then
> the output of the NAND gate will be low so how does INHIBIT get
> activated?
>
Maybe found problem in your logic... when READEN = low0 and R/W=high1 then the output of the NAND gate will be HIGH1.
>
>
> Glenn
379 D input =
(A15 AND A14 AND A13 AND A12 AND A11 AND A10)
AND
( R/W NAND READDIS)
R/W READDIS NAND
0 0 1
0 1 1
1 0 1
1 1 0
So, if R/W is High1 (READ)
and READDIS = low0 (disable Peripheral card RAM)
and address is in range (above AND equation)
then D input on 739 = high1