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Re: Results of Uthernet testing with Apple IIe and SN74LS245N
- Subject: Re: Results of Uthernet testing with Apple IIe and SN74LS245N
- From: a2retro@macgui.com (a2retro)
- Date: Wed, 9 May 2012 14:55:09 +0000 (UTC)
- Newsgroups: comp.sys.apple2
- Organization: Mac GUI
- References: <dog_cow-1334445986@macgui.com> <4652013.1175.1334453387737.JavaMail.geo-discussion-forums@vbhy13> <20638356.266.1334489639813.JavaMail.geo-discussion-forums@vbvi18>
- User-agent: Mac GUI City Usenet Posting
Hi Guys
Michael J. Mahon wrote:
> mwillegal wrote:
>> Hi,
>>
>> PC suffix means plastic DIP package to Fairchild and Moto and perhaps
>> others
>> N suffix means plastic DIP package to TI and many others.
>>
>> So difference is more likely variation between manufacturers, which
>> should not be very significant for LS series parts. Note that
>> differences between the data sheets can be due to variations in
>> manufacturers qualification process. The package type has little bearing
>> on chip performance. Another option to solve the problem may be to look
>> at substituting a different technology pin compatible part, which has
>> more margin for this application.
>>
>> Regards,
>> Mike Willegal
>
> I agree, Mike--any timing differences between manufacturer's LS chips
> should be inconsequential.
"should be" isn't correct in this case. I assumed that as well as my Apple
IIe 80 column card uses a 74LS245PC but upon some investigation I found out
that there are noted differences in the timing between these two parts.
Enough to make a difference as far as gluing a CS8900A to the bus is
concerned anyway.
Prop delay - TI = 8 (max 12) .... Fairchild = 18
OE Enable - TI = 25/27 (max 40/40) .... Fairchild = 25/30
OE disable - TI = 15/15 (max 25/28) .... Fairchild = 25/18
So it would appear the 74LS245PC is to slow in this design as I have had
consistent results using a "N" part in a IIe.
Cheers
Glenn