Re: Results of Uthernet testing with Apple IIe and SN74LS245N

["Michael J. Mahon" <mjmahon@aol.com>]

Michael J. Mahon wrote:
> a2retro <a2retro@macgui.com> wrote:
>
> > Hi Guys
> >
> > Michael J. Mahon wrote:
> >
> > > mwillegal wrote:
> > >
> > > > Hi,
> > > >
> > > > PC suffix means plastic DIP package to Fairchild and Moto and perhaps
> > > > others
> > > > N suffix means plastic DIP package to TI and many others.
> > > >
> > > > So difference is more likely variation between manufacturers, which
> > > > should not be very significant for LS series parts.  Note that
> > > > differences between the data sheets can be due to variations in
> > > > manufacturers qualification process.  The package type has little bearing
> > > > on chip performance.  Another option to solve the problem may be to look
> > > > at substituting a different technology pin compatible part, which has
> > > > more margin for this application.
> > > >
> > > > Regards,
> > > > Mike Willegal
> > >
> > > I agree, Mike--any timing differences between manufacturer's LS chips
> > > should be inconsequential.
> >
> > "should be" isn't correct in this case. I assumed that as well as my Apple
> > IIe 80 column card uses a 74LS245PC but upon some investigation I found out
> > that there are noted differences in the timing between these two parts.
> > Enough to make a difference as far as gluing a CS8900A to the bus is
> > concerned anyway. 
> >
> > Prop delay  - TI = 8 (max 12)             .... Fairchild = 18
> > OE Enable  - TI = 25/27 (max 40/40)  .... Fairchild = 25/30
> > OE disable - TI = 15/15 (max 25/28)  .... Fairchild = 25/18
> >
> > So it would appear the 74LS245PC is to slow in this design as I have had
> > consistent results using a "N" part in a IIe.
> >
> > Cheers
> >
> > Glenn
>
>
> Um, that's Mike Willegal, not me. ;-)

On more careful reading (which, I notice, mobile devices do not
encourage ;-), I did chime in.

I am a bit surprised, but I suppose with the passage of decades
and the inexorable advancement of processes, anyone making LS
(or any similar vintage) chips today is probably getting much
better specs than the originals.

From this, I conclude that the JEDEC specs are "minimum", and
permit "better" specs--with the consequent risks to timing analysis...

After all, you can get into just as much trouble with too fast parts
as with too slow parts--and it all gets serious when they are mixed.
An edge can be too early just as it can be too late.

-michael

NadaNet 3.1 for Apple II parallel computing!
Home page:  http://home.comcast.net/~mjmahon/

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