Re: Test: the cycle

["ict@ccess" <gids.rs@sasktel.net>]

On Feb 16, 7:29 pm, "Michael J. Mahon" <mjma...@aol.com> wrote:
> Steve Nickolas wrote:
> > On Wed, 15 Feb 2012, Michael J. Mahon wrote:
>
> >> I agree, but for backward compatibility, the 50ms trigger approach
> >> was a fine approach--just not perfect.  Now if the "fast/slow" switch
> >> of the IIgs were a simple softswitch, I'd be even happier.
>
> > Though if software is GS-aware and needs to cripple itself to 1 MHz
> > there is a softswitch.
>
> I thought it involved reading a loaction, modifying a bit, and replacing
> it.  So it requires that the accumulator be free.
>
> If there's a one-instruction way, I'd like to know.
>
> -michael
>
> NadaNet 3.1 for Apple II parallel computing!
> Home page:  http://home.comcast.net/~mjmahon/
>
> "The wastebasket is our most important design
> tool--and it's seriously underused."

Have you tried

CLC
ROR $C036

the rest of the bits are not being used in $C036 and this has no
effect on non IIGS computers

Rob