Re: 65c02 in ][+ problem

[david@uow.edu.au (David Wilson)]

Wayne Stewart <waynes@intergate.ca> writes:
>John L wrote:
>> What's the difference between the Rockwell and GTE CPUs ?

>Unfortunately I don't have any knowledge of the differences between
>various brands of 65C02s

There are basically two 65c02 varieties:

1) The one designed at Western Design Centre and fabricated by NCR, GTE
and other manufacturers (I have a 3rd brand which I cannot recall the name
of at present - something Korean I think - HKE?).

2) The Rockwell 65c02 which has extra instructions:

	BBR	#n,zp,addr	branch to addr if bit n of location zp is clear
	BBS	#n,zp,addr	branch to addr if bit n of location zp is set
	RMB	#n,zp		clear bit n of location zp
	SMB	#n,zp		set bit n of location zp

These might be written differently in some assemblers (n=0..7):

	BBRn	zp,addr
	BBSn	zp,addr
	RMBn	zp
	SMBn	zp

This chip is a proper superset of the WDC 65c02 but is not a subset of the
WDC 65802/65816 as the opcodes occupied by the instructions above do something
completely different in the 65802/65816.

>> It's strange that the TransWarp (with the  Rockwell 65c02) can run P8
>> 2.0.3 yet the ][+ with a R65c02 replacement won't.  I've noticed some
>> conflicting reports about which 65c02's will and won't work with P8
>> 2.0.3 on a ][+.  There may be a timing issue with the R65c02 that is
>> addressed properly by the TransWarp card.

According to Jim Sather, only the Rockwell 65c02 will work in an Apple ][+.
The NCR/GTE part requires the data bus to be set up for longer than the Apple
][+ does.

Using the Transwarp the timing would be completely different (the IO slots
would be completely decoupled from the 65c02 - Jim Sather found that the
more loads in the IO slots, the worse the NCR/GTE parts ran).
--
David Wilson  School of IT & CS, Uni of Wollongong, Australia