Re: Apple II Bus Timing

["Arkain" <rwking@usa.nospam.net>]

The sad part is that there really is no specification for the delay between
the fall of o0 and o2. If you want a figure to run by, then you may have to
do some experimenting. You should be safe using 10ns as an over-guess for
the delay between the 2 signals. If you really need to be safe, just wait
for the first edge of the 7M signal that follows the fall of o0. That should
cover both the required 10ns wait as well as the delay between o0 and o2.

Hope this helps

Arkain

"Andrew Quinn" <andrew.q@ihug.co.nz> wrote in message
news:8soken$5un$1@news.ihug.co.nz...
> I have been puzzling over some strange timing related issues on my IDE
> controller board for some time and while at the local surplus electronics
> store picked up a book called "The Apple II Circuit Description" by
Winston
> Gayler.  In this book I find a caution for designers that basically says:
>
> "The 6502 data sheet specifies that at the end of a read cycle the data
must
> remain stable on the 6502 inputs for a 10ns hold time after the 6502 o2
> clock falls."
>
> The apple bus provides o0 (rather than o2) for bus timing and this appears
> to lead o2 due in the timing diagrams but I cannot find timing details of
> this lead so I can hold the data on the bus a little longer.
>
> Does anyone have any ideas?
>
> Regards...... Andrew
>
>
>