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Re: 65c02 VHDL

"Scott L. Baker" writes ...
> 
> I have written a 65c02 VHDL model and synthesized it.
> It fits into an Altera 10k30, but I can generate edif netlist
> files for a number of different FPGA families.
> I want to keep IP ownership of the VHDL, but I may be
> willing to supply edif netlist files to people who want to
> build prototype hardware.  Contact me if you are interested
> and we can discuss the details.
 ....

     Interesting project! How fast would your 65C02-on-10k30 be?


Rubywand