Re: 65c02 VHDL

[CUTblakeney@home.com (Jeff Blakeney)]

On Fri, 14 Jan 2000 01:48:24 -0800, "Scott L. Baker"
<scd@teleport.com> wrote:

>I have written a 65c02 VHDL model and synthesized it.
>It fits into an Altera 10k30, but I can generate edif netlist
>files for a number of different FPGA families.

I would understand this message a lot more if I knew what VHDL, Altera
10k30, edif netlist and FPGA were.  :-)

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