Re: Ram Question

[dempson@actrix.gen.nz (David Empson)]

Supertimer <supertimer@aol.com> wrote:

> dempson@actrix.gen.nz (David Empson) wrote:
> 
> >If the card has 8 rows (2 MB using 256 KB per row, or 8 MB using 1 MB
> >per row) then it has to bend the rules a little, but can still use the
> >FPI to do refreshing.  (It may lose DMA compatibility.)
> 
> The Sirius is completely DMA compatible with the RamFAST
> revision D card but has some problems with DMA and the
> Apple High Speed SCSI card.  Why is that?

OK, lets start with the normal situation and ignore the RamFast.

The 65816 extends the address bus of the 6502 family by outputting a
bank address on the data bus during the first half of the clock cycle.

In the IIgs, the FPI chip latches the bank address, and decodes it to
identify which memory area the CPU is addressing.  For banks $00 and $01
on the original motherboard ($00 through $0F on the 1MB motherboard) the
appropriate row of RAM on the motherboard is selected.

The memory expansion card occupies the next range of banks.  A signal on
the slot tells the FPI whether the card is using 256KB or 1MB per row.

The FPI decodes the bank address to generate a two-bit row select
signal, and combines the bank address with the normal 16-bit address to
generate a multiplexed 18-bit or 20-bit row/column address for the
memory expansion card.

The memory map is as follows for the original IIgs motherboard:

   256 KB rows              1 MB rows
CPU Bank     Row        CPU Bank     Row
$02 - $05     0         $02 - $11     0
$06 - $09     1         $12 - $21     1
$0A - $0D     2         $22 - $31     2
$0E - $11     3         $32 - $41     3

For the 1 MB IIgs motherboard, the map is:

   256 KB rows              1 MB rows
CPU Bank     Row        CPU Bank     Row
$10 - $13     0         $10 - $1F     0
$14 - $17     1         $20 - $2F     1
$18 - $1B     2         $30 - $3F     2
$1C - $1F     3         $40 - $4F     3

The memory expansion card is connected directly to the main CPU data
bus, so it also has direct access to the bank address which was placed
on the data bus by the CPU.  If the card is going to support an unusual
configuration, or more than 4 MB (1 MB if using 256 KB rows) then it
must decode part of the bank address from the data bus.

Some cards decode the bank address fully, and ignore the row select
signals.  These card may need to implement their own memory refreshing,
and are not compatible with DMA (see below for explanation).

Most cards use the row select in conjunction with a single bit from the
bank address, to extend the memory expansion card space to nearly 8 MB
(actually 8 MB minus the amount of RAM on the motherboard).

Using the A22 signal ($400000) allows the card to determine whether the
CPU is addressing banks $00-$3F or $40-$7F.  This is combined with the
row address to form an extra row select signal.

(Banks $E0 and $E1 are directed to the Mega II "slow RAM" area, banks
$F0-$FB or $FD are available to the memory expansion slot for use as a
ROM disk or ROM expansion, and banks $FC or $FE to $FF are motherboard
ROM.)


Now for the other parts of the equation.

First, the issue of refreshing: the FPI generates refresh addresses
using the multiplexed address bus.  This has to be recognised by the
card and it needs to refresh all rows in parallel.  If the card has an
unusual geometry, it may not be able to rely on these signals to refresh
all its RAM.

Secondly, the issue of DMA.  In a DMA cycle, the CPU is disconnected
from the address and data busses, and is frozen.  The DMA address is
generated directly by the card (lower 16 bits) and from the DMA BANK
register in the FPI.  The bank register is used in the same manner as
the CPU bank address to determine the memory area being accessed
(motherboard RAM, memory expansion slot RAM, slow RAM, memory expansion
slot ROM, or motherboard ROM).  For memory expansion slot RAM, the same
row select and multiplexed address described above is generated.

The catch: the bank address is _not_ output onto the data bus.  If the
memory expansion card is expecting a bank address to be provided, then
it may latch a random value instead of the appropriate address.  This
causes it to perform DMA to the wrong bank, causing memory corruption
(and loss of the data being transferred).

Thus any card which relies on the row select signals (and is limited to
four rows) will be fully DMA compatible.  Any card which depends
partially on the bank address will not be DMA compatible.


The RamFast uses a special technique to allow DMA to cards that (in
theory) don't support DMA.  I don't know exactly how it manages this,
but I suspect it involves getting the CPU to access memory in the
appropriate bank (so that it outputs a bank address on the data bus)
before freezing the CPU and performing the DMA transfer.

-- 
David Empson
dempson@actrix.gen.nz
Snail mail: P O Box 27-103, Wellington, New Zealand