[no subject]

>>

Apple II+/IIe Power Supply Socket


 II+/IIe Power Supply Socket      Power Supply Output Ratings
         _________
        /         \               +5V @ 2.50 Amps (continuous)
  -12V  |  5   6  |   -5V         -5V @ 0.25 Amps (continuous)
        |         |              +12V @ 1.50 Amps (continuous)
   +5V  |  3   4  |  +12V        -12V @ 0.25 Amps (continuous)
        |         |
   GND  |  1   2  |   GND
        |_________|




___________________________



Apple 16-pin DIP Game Port socket (on the motherboard)
  for II, II+, IIe, IIgs


                           =========
Pushbutton 3 (GS only)  9 | *     * | 8  Ground
 Gm Ctrl 1 (Stick-1 Y) 10 | *     * | 7  Gm Ctrl 2 (Stick-2 X)
 Gm Ctrl 3 (Stick-2 Y) 11 | *     * | 6  Gm Ctrl 0 (Stick-1 X)
        Annunciator 3  12 | *     * | 5  /$C040 Strobe
        Annunciator 2  13 | *     * | 4  Pushbutton 2
        Annunciator 1  14 | *     * | 3  Pushbutton 1
        Annunciator 0  15 | *     * | 2  Pushbutton 0
        No Connection  16 | *     * | 1  +5V
                           ===| |===
                               ^
                        Notch on socket
                (faces toward front of computer)



___________________________




Apple II/II+ Keyboard Socket Pinout


         +---| |----+
    +5v  | 1     16 | NC
 Strobe  | 2     15 | -12v
 ~Reset  | 3     14 | NC
     NC  | 4     13 | Data 1
 Data 5  | 5     12 | Data 0
 Data 4  | 6     11 | Data 3
 Data 6  | 7     10 | Data 2
    Gnd  | 8      9 | NC
         +----------+

Pin        Name    Description

1          +5      +5 volt power supply.  Total current drain on this pin must
                   be less than 120mA.

2          STROBE  Strobe output from keyboard.  This line should be given a
                   pulse at least 10 microsecond long each time a key is
                   pressed on the keyboard.  The strobe can be of either
                   polarity.
           _____                    _____
3          RESET   Microprocessor's RESET line.  Normally high, this line
                   should be pulled low when the <RESET> key is pressed.

4,9,16     NC      No connection.

5-7,10-13  Data    Seven bit ASCII keyboard data input.

8          Gnd     System electrical ground.

15         -12v    -12 volt power supply.  Keyboard should draw less than
                   50mA.


___________________________


<<





     This is information about Apple II Slot pin functions (from the Csa2
Csa2HDWHACK FAQs file):


>>

From: David Empson

004- What is the pin-out for the Apple II series Slots; and, what 
     differences are there in Slot signals from machine to machine? 

Here is a quick summary of the Apple II series Slot signals: 

Pin 1: I/O Select ($Cn00-$CnFF, where n is the slot number). 

Pins 2-17: Address bus A0-A15. 

Pin 18: Read/Write. 

Pin 19: unused on the II and II+.  On the IIe and IIgs, this has composite 
horizontal and vertical sync on slot 7, and is unused on other slots, except 
for slot 1 on the IIe only, which has a diagnostic function to disable the 
oscillator on the motherboard. 

Pin 20: I/O Strobe ($C800-$CFFF). 

Pin 21: this is the RDY input to the micro on all machines, but it behaves a 
little differently in the IIgs, or in a machine with a 65802 installed. 

Pin 22: this is the DMA pin on all machines.  Again, there are special issues 
for doing DMA on the IIgs which can cause compatibility problems. 

Pin 23: this is used for the interrupt daisy chain (out) on all Slots except 7. 
In the IIe only, this pin can be connected to the GR signal (graphics mode 
enabled) via a motherboard modificatoin. 

Pin 24: DMA daisy chain out. 

Pin 25: +5V. 

Pin 26: Ground. 

Pin 27: DMA daisy chain in. 

Pin 28: Interrupt daisy chain in. 

Pin 29: Non Maskable Interrupt. 

Pin 30: Interrupt Request. 

Pin 31: Reset. 

Pin 32: this is the INHIBIT pin on all machines.  This behaves differently on 
all three machines: the II and II+ only allow the $D000-$FFFF ROM area to be 
inhibited.  The IIe allows RAM to be inhibited as well, but has strange 
interaction with main and auxiliary memory.  The IIgs only allows this signal 
to be used if the machine is running in slow mode. 

Pin 33: -12V. 

Pin 34: -5V. 

Pin 35: unused on the II and II+.  On the IIe and IIgs, this is the colour 
reference signal on slot 7 only.  It is unused for other slots in the IIe, 
except for slot 1 where it provides a poorly documented facility to disable the 
keyboard address decoding.  On the original IIgs, slot 3 provides the M2B0 
signal (Mega II Bank 0) via this pin and it is unused on other slots.  The ROM 
3 provides M2B0 for slots 1 to 6. 

Pin 36: 7 MHz system clock. 

Pin 37: Q3 - Asymmetrical 2 MHz clock. 

Pin 38: Phase 1 clock (1.023 MHz). 

Pin 39: something called "USER 1" on the II and II+, which can be used to 
disable all I/O decoding if a modification is made on the motherboard.  On the 
IIe, this pin provides the SYNC signal from the micro, which indicates an 
opcode fetch.  On the IIgs, this pin provides the M2SEL signal, which indicates 
that a valid slow memory access is in progress.  This pin must be used by IIgs 
cards that decode the address without use of the IOSEL, IOSTRB or DEVSEL pins. 

Pin 40: Phase 0 clock (1.023 MHz). 

Pin 41: Device Select ($C0n0-$C0nF, where n is the slot number plus 8). 

Pins 42-49: Data bus D7-D0. 

Pin 50: +12V. 







Rubywand