Re: 6502, 65816 = RISC ?

[wbaguhn@nyx10.cs.du.edu (Will Baguhn)]

In article <nugundamDw9wxq.GEy@netcom.com>,
Joseph Lee <nugundam@netcom.com> wrote:
>Nathan Mates (nathan@visi.com) wrote:
>:    For the third time in as many days, it's THE WAY THE PROCESSOR
>: ACCESSES THE BUS. Not pipelining. Electrically, the 6502 takes 1 (one)
>: clock cycle to read a byte off the bus. The 8086 takes 4 (four). Thus
>: for _ANY_ memory access, the 6502 is 4 times faster than an 8086 at
>: the same clock speed to read that byte. 
>
>Can you explain what exactly each chip is doing during those cycles when
>it is pulling something off the bus?  Might as well as explain what the
>68000 does at the same time too, because it requires 4 cycles per word (or
>used to).
>
>I always though it was because the 65xxx series did some preprocessing so
>that it could pull stuff off the bus in 1 cycle and that could be called
>pseudo-pipelining in terms of executing an instruction and do processing to
>prepare for the next one.  Of course, it doesn't quite explain why 1 byte/no
>memory access instructions take 2 cycles to execute.
>-- 
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Sure it does... I haven't looked at a timing sheet recently, but I think that
it doesn't know what the instruction byte is until the end of the first cycle.
That means that it can't start working on it until cycle 2.

So.... if we uniformly subtract 1 fetch cycle per opcode, we get instructions
running in 1 cycle.  ;)
-- 
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