Although Verilog *looks* like software, it's really hardware--it can be quite a leap from sequential programming to "everything happeningat once, on each clock pulse". ;-)Yeah, that's a big mental hurdle. In a way I wish they hadn't tried to make it "look" like a software language.
Both Verilog and VHDL were designed for simulation which is *almost* a programming thing. It just so happened that they became very useful for synthesis.
-Alex. --- news://freenews.netfront.net/ - complaints: news@netfront.net ---