[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: Dead GS
In article <4uib0n$ir1@nyx10.cs.du.edu>, wbaguhn@nyx10.cs.du.edu (Will
Baguhn) wrote:
>In article <dempson-0808960145070001@dempson.actrix.gen.nz>,
>David Empson <dempson@actrix.gen.nz> wrote:
>>Yes, but the ZIP still fails one of the later tests (most of the time), so
>>I don't see that it achieves very much to enable this option. I was
>>trying to avoid too much detail. It is easier to just disable the ZIP
>>before running the test, if you want a reliable result. It also avoids
>>any speed penalties from leaving the "fix test 5" option enabled all the
>>time.
>
>I've never had this problem. Perhaps your Zip is flakey?
Both of them, in two different IIgses?
This is documented in the ORIGINAL manual for the ZIP (which also explains
what all the switches do). I quote from page 3:
"NOTE: Unless the ZipGS is diabled, it will, AT TIMES, fail the Apple IIgs
internal test 0BXXXXXX (as this test depends on 2.8 MHz speed). The ZipGS
will also fail internal test 0CXXXXXX. THIS IS NOT AN ERROR."
On page 4, it also mentions that the IIgs will fail test 05XXXXXX unless
SW1/4 is set OFF (counter delay enabled).
Every time I have bothered to try (including just now), I get a "System
Bad: 0B0300000" result, UNLESS the ZIP is disabled. I usually have the
counter delay disabled, so I rarely get this far, getting a failure on
test 05XXXXXX instead.
I just tried the test again with the ZIP GS disabled, and it passed with
flying colours (boy, it really takes a long time!)
>Also, that speed hit is outweighed by the fact that some programs need
>to lock on to that timing signal to display properly... so turning off
>the delay makes the timing wrong, and can screw up display.
If the program is using the horizontal counter to get a timing reference,
then it will work just fine whether the ZIP is accelerated or not. It
will just get to execute more instructions between synchronization points.
On the other hand, if the program is relying on CPU execution speed being
in sync with a detected reference point, then it is going to misbehave.
--
David Empson
dempson@actrix.gen.nz
Snail Mail: P.O. Box 27-103, Wellington, New Zealand
- References:
- Dead GS
- From: krinibar@aol.com (Krinibar)
- Re: Dead GS
- From: dempson@actrix.gen.nz (David Empson)
- Re: Dead GS
- From: wbaguhn@nyx10.cs.du.edu (Will Baguhn)
- Re: Dead GS
- From: dempson@actrix.gen.nz (David Empson)
- Re: Dead GS
- From: wbaguhn@nyx10.cs.du.edu (Will Baguhn)