Re: Thoughts on 8-bit acceleration.

[dempson@actrix.gen.nz (David Empson)]

Iosaef the Irascible <josefcub@gmail.com> wrote:

> On May 5, 4:00 am, demp...@actrix.gen.nz (David Empson) wrote:
> > Not trying to put you off, but some points to consider...
> 
> That's precisely the reason why I asked, and by your reply I'm fairly
> confident I'm not smart enough to pull it off.  It was enough that I
> had a 6502 talking on a breadboard and came up with the lame-brained
> scheme to begin with. ;-)
> 
> > Probably in CPLD or FPGA territory to get a reasonably compact
> > implementation of the logic.
> 
> At that point, you could build the entire 65C02 core in the FPGA along
> with the memory, and accelerator logic.   Save a mess of chips, too.
> I'm not trying to get into the "purity" argument, but the modern FPGA
> does seem to lend itself to that idea quite well.  And it would be
> quite an acid test for an FPGA core if it could successfully run a
> real Apple II's software AND hardware.
> 
> Thanks for your input though, it does shed a lot of light on the parts
> of the hardware I don't know at all, and why my 8-bit Transwarp has so
> many chips on it, including the PALs.
> 
> Though, how did the RocketChip and ZipChip manage to do it?  I know
> they had some cache on-board, but that's about all I know of the
> theory of how they operated.

They don't duplicate the memory of the Apple II. Instead they have a
write-through cache (8 KB in the Zip Chip, I think). Writes always go to
real memory (thus slow down to 1 MHz), and reads come from the cache as
long as the appropriate location has been read or written recently (thus
can operate at 4 MHz for repeated reads).

The ZipGS uses a similar architecture but can be configured with up to
64 KB of cache.
-- 
David Empson
dempson@actrix.gen.nz