Re: Thoughts on 8-bit acceleration.

[mdj <mdj.mdj@gmail.com>]

On May 5, 11:45 pm, demp...@actrix.gen.nz (David Empson) wrote:

> They don't duplicate the memory of the Apple II. Instead they have a
> write-through cache (8 KB in the Zip Chip, I think). Writes always go to
> real memory (thus slow down to 1 MHz), and reads come from the cache as
> long as the appropriate location has been read or written recently (thus
> can operate at 4 MHz for repeated reads).

Michael and I performed some simple benchmarking a few years back
(should be easy to find the thread) that suggested that the Zip Chip
actually does buffered asynchronous writes, ie. a write-back cache. As
long as code is executing from a cached page, it is free to use the
main bus to write back cached data on every cycle and it seems that in
practice this scheme works beautifully.

I had postulated that the original Transwarp would be slightly faster
clock-for-clock than a ZipChip due to never having to incur a cache
invalidation. As it turns out, even for simple cases this isn't true.

IIRC, the Transwarp uses its 256kb of fast ram to replace the two 64k
banks, ROM, and to cache the currently selected bank on a RamWorks
card. Even with all that it's still vastly inferior to the Zip design.

Matt