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Re: Carte Blanche templates for xilinx ISE?



rich12345 wrote:
On Apr 6, 5:34 am, Steven Hirsch <snhir...@gmail.com> wrote:
substituted into into the stock verilog sources?

Everything on applelogic seems to be for altium...

Can you guys set up a page detailing:

1)which pins on fpga go to :
  apple bus
  IDE connector
  flash connector

Alex Freed made some directories available that had workable ISE sources. There was a small configuration change required for the 10.1 and 11.1 ISE, but it was push button aside from that.

In those sources, the file 'cb.ucf' contains the top-level mapping between FPGA pins and the CB itself. With that and the CB schematics (available from AppleLogic) you should be able to figure out the entire picture. I agree that there should be a "one-stop-shopping" document for this, but I think Alex and Steve have only so many hours available in a day :-).

Add these lines to then end of cb.ucf:

NET "BUS_Q3" CLOCK_DEDICATED_ROUTE = FALSE ;
NET "BUS_PHASE0" CLOCK_DEDICATED_ROUTE = FALSE ;

in order to soften up two errors that would otherwise prevent it from compiling.

Steve