Re: Carte Blanche templates for xilinx ISE?

[rich12345 <aiiadict@gmail.com>]

On Apr 6, 6:05 pm, Steven Hirsch <snhir...@gmail.com> wrote:
>
> Alex Freed made some directories available that had workable ISE sources.
> There was a small configuration change required for the 10.1 and 11.1 ISE, but
> it was push button aside from that.


Can you post a link?

>
> In those sources, the file 'cb.ucf' contains the top-level mapping between
> FPGA pins and the CB itself.  


I can't find any .ucf files on applelogic.org


>With that and the CB schematics (available from
> AppleLogic) you should be able to figure out the entire picture.

I could do most of it from the schematics, I was hoping there was a
conversion tool from altium--->xilinx templates.

> I agree that
> there should be a "one-stop-shopping" document for this, but I think Alex and
> Steve have only so many hours available in a day :-).

If I can find out enough to get it going, I'll send Alex and Steve a
document describing how to do it/where to get information.


>
> Add these lines to then end of cb.ucf:
>
> NET "BUS_Q3" CLOCK_DEDICATED_ROUTE = FALSE ;
> NET "BUS_PHASE0" CLOCK_DEDICATED_ROUTE = FALSE ;
>
> in order to soften up two errors that would otherwise prevent it from compiling.
>


Post a link where I can find the directories that Alex made available
please?


Rich