Re: ZIP Chip Heartbreak

[gtolar@blkbox.com (Glynne Tolar)]

David Empson (dempson@atlantis.actrix.gen.nz) wrote:
: You hit the nail on the head with DMA being the problem, but you have
: the wrong idea about _why_ it is a problem.

: DMA compatibility has nothing to do with speed.  The problem is that
: DMA works by controlling several signals available on the slots which
: cannot be detected by the microprocessor (they are handled by external
: circuitry).  In a DMA cycle, a byte is transferred directly from
: memory to the slot peripheral (or vice versa) while the processor is
: disconnected from the bus.

: As a result of this, the ZIP doesn't see the memory access taking
: place, and cannot cache the data.  If it has previously cached the
: memory area which you do a DMA READ into, subsequent accesses to that
: area will read the old (incorrect) data from the ZIP's cache.  The end
: result is corrupted data, and usually a crash.

: To avoid this, you must either disable the ZIP or disable DMA on the
: SCSI card.

: This is only a problem with the ZIP Chip, Rocket Chip and Transwarp IIe
: (and probably older accelerators such as the Speed Demon).

: The ZIP GS and TransWarp GS are on a card, and have access to the slot
: signals that control DMA cycles, so they can detect and correctly
: handle them.

: In theory, the same could be said for IIe card-based accelerators such
: as the TransWarp IIe, but none of them implement DMA support.

I realize this is dreaming here but even though the CPU pins don't 
receive the data accessed by a DMA device (I'm not so sure the thses 
signals don't make it to the CPU pins, but never the less are not 
supported by all //e accelerators) couldn't the CPU when it detects a DMA 
signal (that I know makes it to the CPU!) just flush its cache?  I know 
you'ld have some speed loss.  Just a thought.