Re: ZIP Chip Heartbreak

[dempson@atlantis.actrix.gen.nz (David Empson)]

In article <dd84481@pro-nsdapple.cts.com>,
Jeff Goodman <express@pro-nsdapple.cts.com> wrote:
> [snip]
> Well, one of the first things I very quickly found out, is the DMA
> thing the HS SCSI card does (I got a clue from reading the Tech Notes) 
> anyway, I learned that DMA transfers are very timing dependent.

You hit the nail on the head with DMA being the problem, but you have
the wrong idea about _why_ it is a problem.

DMA compatibility has nothing to do with speed.  The problem is that
DMA works by controlling several signals available on the slots which
cannot be detected by the microprocessor (they are handled by external
circuitry).  In a DMA cycle, a byte is transferred directly from
memory to the slot peripheral (or vice versa) while the processor is
disconnected from the bus.

As a result of this, the ZIP doesn't see the memory access taking
place, and cannot cache the data.  If it has previously cached the
memory area which you do a DMA READ into, subsequent accesses to that
area will read the old (incorrect) data from the ZIP's cache.  The end
result is corrupted data, and usually a crash.

To avoid this, you must either disable the ZIP or disable DMA on the
SCSI card.

This is only a problem with the ZIP Chip, Rocket Chip and Transwarp IIe
(and probably older accelerators such as the Speed Demon).

The ZIP GS and TransWarp GS are on a card, and have access to the slot
signals that control DMA cycles, so they can detect and correctly
handle them.

In theory, the same could be said for IIe card-based accelerators such
as the TransWarp IIe, but none of them implement DMA support.

-- 
David Empson
dempson@actrix.gen.nz
Snail mail: P.O. Box 27-103, Wellington, New Zealand