6502 CPU

[jeff.brielmaier@yob.com (Jeff Brielmaier)]

WB>| Does any of you know about the undocumented instructions on the 6502 ?
WB>| Thanks.
WB>
WB>you mean like HCF?

Only on 6800's and real-old 6502's <vbg>

I belive that he is referring to X7 and XF opcodes.

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Byte    December 1977         Technical Forum           Page 72

The XF and X7 Instructions of the MOS Technology 6502

HT Gordon
Dept of Entomological Sciences
110 Wellman Hall
University of California
Berkeley, CA  94720


None of the operation code listed in the instruction set of the MOS
Technology 6502 has a low order bit pattern of 1111 (hexadecimal F) of
0111 (hexadecimal 7), although many have 1110, 1101, 0110 or 0101.
How does the processor interpret op codes of type XF or X7 where X is
an arbitrary high order digit?

When I tried this out I found that it executes them as valid
instructions to do *both* the XE and XD, or *both* the X6 and X5
instructions, with fascinating and useful results.  Thus for example
A5 XX causes a load of the byte in page zero location XX into the 
accumulator, A6 XX loads this byte into the X register, and A7 XX 
loads it into *both* index registers, an operation that would require 
three program bytes with the conventional coding.

Op code 87 is even more interesting,  since 85 XX stores the value in 
the accumulator into page zero location XX and 86 XX stores the value 
in the X register into XX, and it is obviously impossible to store two 
different values simultaneously in one location.  The effect of 87 XX 
is to store into location XX only those 1 bits that occur in *both* 
the accumulator and the X register.  The effect is that of a logical 
AND between the accumulator and the X register (neither is one being 
altered), with storage of the result into XX.

The effect of 97 XX resembles that of 87 XX, except that the result of
the AND is stored in page zero location XX + Y, since Y indexed
storage is used by op codes 95 and 96.  Since these are store
instructions, no testable flags are set.  In general, op codes of type
XD and XE have the same logic as X5 and X6, differing only in having a
2 byte absolute address instead of a 1 byte page zero address.  This 
is not true for op codes of type 9X.  Both are nevertheless executed, 
but the operations are not the same as those of 96 and 97.  The 
resemble the valid 9D in that storage into Y indexed absolute address 
(XXXX + Y) is commanded.  However, 9E stores the result of the AND 
between the byte in the X register and the hexadecimal immediate value 
of 02, ie: if bit 1 of this byte is a 1, 02 is stored, and if not, 00 
is stored.  (I have no idea where the processor finds the 02.)  Op 
code 9F stores the result of an AND between the value 02, the X 
register, and the accumulator; if the bytes in *both* registers have a 
1 in bit 1, 02 is stored; otherwise 00 is stored.

When X5 and X6 command different operations, X7 causes X6 to be done 
first, followed by the X5.  For example E7 XX causes the byte in XX to 
be incremented by 1, then subtracts this value from the accumulator, 
setting the proper flags and leaving the result in the accumulator.  
Everything the "new" instructions do could of course also be done with 
conventional set, using more program bytes and time.  Most of the 
unused op codes of the 6502 "run", but 12 of type X2 cause operations 
to become "lost in space," from which only RESET can rescue them.  It 
would be interesting to know whether some of the unused op codes of 
the other microprocessor designs will also prove to be valid 
instructions.

Since discovering the XF and X7 instructions, I have found that there 
are also "unofficial" XB instructions.  For example A9 XX is a load 
immediate of the byte XX into the accumulator, and AA commands 
transfer of the byte into the accumulator into the X register.  The 
effect of AB XX is to load XX into *both* the accumulator and X 
registers, setting the usual flags.  Some other XB op codes are also 
executed, but I have not yet had time to work out their operation.  I 
have no doubt that some of these instructions could be put to use, but 
there is a hazard.  If manufacturers decide to add new *planned* 
instructions in chip redesign, programs using the unplanned ones will 
be incompatible.

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* KingQWK 1.05 # [PK] * Honest teacher - A virus ate my homework !

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