Re: WDC Chip Order Update

[o9938156@wsuaix.csc.wsu.edu (mark lyon)]

cdeschu@nyx10.cs.du.edu (Chris Deschu) writes:
: In article <39ku92$o1f@news.service.uci.edu>,
: Trangdaithi Hoang <thoang@orion.oac.uci.edu> wrote:
: >In article <39kqhj$oif@blackice.winternet.com>,
: >Frank M. Lin <fmlin@icicle.winternet.com> wrote:
: >
[snip]
: 
: Hmm, this is interesting. My Engineering part won't go over 10mhz
: reliably, and I have fast ram and gals. I have avoided buying one

The E parts are only rated at 10MHz.  You can push them by increasing
the supply voltage.  The 14MHz chips are rated at 14MHz, but need
to be in the proper environment, i.e. if the cache or other chips
draw too much current so the voltage on the lines drop below the
threshold, the chip won't run reliably.

: of the new 14mhz chips because of nightmare stories like this.
: Could you please tell the unenlightened of us *exactly* how to go
: about "buffering" the I/O lines? I did take some electronics
: courses, but I'm not familiar with what you are saying. In case you
: have not guessed, I have a TransWarp GS, but I'm sure the information
: would be useful to those with ZipGS' too. Thanks!
: 
I would assume that buffering the io lines means putting a voltage
follower or similar device (i.e. an AND gate with one input tied
high. I'm sure there are dedicated buffers available too) between
the cpu and the cache.  This would allow the io lines to source
more current.  Incidentally, is this why low power cache ram
chips seem to work better in zips?  In other words, do the inputs
of LP chips draw less current than those of non-LP chips?
Anyway, the buffering would probably require quite a bit of
trace cutting and some extra wires on the board:  doable, but
rather involved, IMHO.

Mark Marr-Lyon
o9938156@wsuaix.csc.wsu.edu