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Re: Fastest TWGS and ZIP GS
In article <28q93k$sh@r-node.io.org>, Brian Tao <taob@io.org> wrote:
>In article <arkrauss.0a18@lsd.nbg.sub.org>, Alexander Krauss writes...
>>
>> From which speed have I to higher the 5V Vcc Voltage ? I can also rember
>> that the WDM samples have printout of MHz/Vcc ...
>
> Why do you need to increase the voltage to make a chip go faster?
>Why isn't it enough to simply pump up the speed of the crystal? I know,
>simply question, complex answer... :)
It has to do with logic levels and switching rates, and isn't too complicated
if you know a bit of physics. Basically there's a certain amount of
inductance (and capacitance, but usually the problem's inductance related) in
an electric circuit. Just a single trace on a circuit board creates
inductance. Since logic signals are normally square wave signals (0 or +5v
only) inductance tends to curve the front end of the square wave. That's not
noticable at low frequencies, but at high frequencies it becomes a problem.
It's hard to show without a graph, but the current through an inductor (and
corresponding voltage at the load) is given by (1-exp(-t*R/L)) times the
appropriate constants. Notice that as t gets large (low frequencies) the
number aproaches one. For higher frequencies, a point is reached where the
voltage level at the load will not have made the full transition from 0 to +5v
or vice versa before the logic level at the source changes to a new value.
The way around this problem (assuming the source circuitry can handle it) is
to boost the operating voltage of the source. Thus, instead of the source
causing a transition from 0 to 5v, it'll be a transition from 0 to 6v, and
thus the load (other chips in the system) will reach a logic high (usually
about 3.5v) state within the given amount of time, whereas they wouldn't
have otherwise.
I'll attempt to illustrate here...
______________ _________
| | / |
| | / Something | --- Logic high
| This pulse | / like this \ level.
| at the | Becomes.... / pulse at the \
| source... | | load... \
____| |________ _____| \_ --- Logic low
If we increase the frequency we get:
___
| | Becomes something like
| | this at the --- Logic high
| | This pulse load. / \ level.
| | at the / \
| | source... | \
____| |____________ _____| \_ --- Logic low
Notice that it never reached the logic high point.. And if there was
another transition high following that, it would never have gone back
to the logic low point either, so there can be errors due to transitions
in either direction...
However, if we increase the supply voltage....
___
| | Becomes something more like
| | this at the load!
| | /|
| | / | --- Logic high
| | This pulse / | level.
| | at the | \
| | source... | \
____| |____________ _____| \_ --- Logic low
So we still get a suitable logic transition at the higher frequency.
Well, damn, this did become a long winded discussion anyway, but maybe
that'll help people understand why the change in supply voltage allows
the CPU to be pushed to higher frequencies.
>--
>Brian Tao:: taob@io.org (Internex Online, 416-363-3783, 17 lines, v.32bis)
>::::::::::: 90taobri@wave.scar.utoronto.ca (University of Toronto, 9T4)
>
Michael Foegelle
--
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