At the same time the re-configuring is a little dangerous just like re-flashing a motherboard BIOS. If something goes wrong during the procedure - a power failure or some other malfunction - it can "brick" the board and the only way to unbrick will be by using the $12 JTAG tool. Or a $300 USB JTAG from Xilinx :)I am a little worried about the potential failure mode for those who would hack it, or even those who hope to reconfigure it frequently...
The hackers are in no danger - the JTAG cable is a must and works every time without any need to reprogram the flash.
Reconfiguring the flash frequently should definitely be avoided.
It seems that many FPGA-based designs have this issue. Perhaps there should be a notion of "banking" in FPGAs, so that they can be partially reconfigured, even under control of temporarily "locked" banks. As they get larger and larger, and therefore slower to fully configure, this seems an inevitable issue.
Indeed. It has occurred to me that since the bit stream starts with an 8 byte "synchronization header" it may be possible to send FFs before this header. Just a guess not confirmed by anything yet. If that is indeed true, we can have a reserve configuration starting at page 6. Then if the first 5 pages (that normally contain the configuration) are erased, this fallback configuration will become operational, but again I don't know if this will work. In real life I usually throw a $1.50 microcontroller at the problem that will always be ready to re-program the firmware or the FPGA configuration if shit hits a fan.
-Alex.