vladitx wrote:
Right now the NTSC table approach is impractical for the FPGA because of the big table size, but I will try reducing them as fitting into FPGA was one of the main goals when I started it. How many BRAMs do you want to spare and what is the DAC resolution? BRAM in x9 width seems practical to me, then you can have 3 bits per color component.
We only have 2 bits per color but with a lot of vertical resolution lines be can emulate another bit by dithering. But I guess it's not worth the trouble. GS look is good enough for me :)
-Alex.