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Re: Carte Blanche



sicklittlemonkey wrote:
On Apr 4, 7:47 am, "Michael J. Mahon" <mjma...@aol.com> wrote:
Nick, to capture the bitstream it is only necessary to continue
to shift read data into the shift register continuously, then
sample it (by loading it and storing it into memory) often enough
that no bits are unobserved.  The Apple's speed is sufficient to
do this without a problem.

Yes, but I was trying to do this at better than 4-CPU-cycle resolution
to reliably capture time-sensitive parts of the stream (including sync
nibbles of course).

The best results I had were at the highest resoltion possible: 2
sequencer clocks = 1 CPU clock. The read pulise line is shifted into
the latch at this rate, which means a full latch every 8 CPU clocks.
So load, store, load, store ... ;-)

That's what I meant about bandwidth and memory. There's not enough
main memory to store an entire track's this high resolution data, and
the CPU is too busy to do anything else. Even on the GS. Running this
data through an emulation of the normal sequencer looks good though.

Since the maximum transition rate is once every 4 microseconds, you
don't need to sample that often--you just need to arrange not to
miss a pulse.  Any sub-bitcell timing variation will not be able
to be repeatably determined by *any* Apple II code, so no protection
scheme can depend on it either.

The thing that *is* necessary, and that the EDD+ allowed, is
determining the presence of extra zero bitcells between valid
nibbles.

The state machine samples at 2MHz because a read pulse is nominally
only 1 microsecond wide, and 1MHz sampling might miss one.  The
higher sampling rate also allows finer grain adjustments of the
"digital PLL" to stay in sync with bitcells.

But there is still a limit of one pulse per 4 microseconds, so
the shift rate can be kept to 250kHz--so there's plenty of time
to load the shift register value and store it every 4 bitcells,
even using a loop.

-michael

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