Re: IIgs peculiarities

[dempson@actrix.gen.nz (David Empson)]

vladitx <vladitx@nucleusys.com> wrote:

> On Feb 25, 1:30 am, demp...@actrix.gen.nz (David Empson) wrote:
> 
> > It appears that the monitor always forces fast mode while it is active
> > ($C036 contains $80), no matter what the Control Panel says.
> 
> I think I remember 'L'isting in Monitor at (visually) slow and fast
> speed after changes through Control Panel. Could it be that only key
> waiting is switching to fast mode?

I'd have to do more tests and don't have time in the next few days.

> > The monitor saves the speed register on entry (e.g. CALL -151 or when a
> > program executed with G returns) and restores it on exit (e.g. when you
> > use a G command or Ctrl-C).
> >
> > It also saves the speed register and temporarily forces fast mode while
> > waiting for input, so if you use the Control Panel to change the speed
> > while at a prompt in BASIC, it doesn't stick immediately.
> 
> Any faintest idea why speeding while waiting for keypress? It's beyond
> me, totally.

The only reasons I can think of would relate to the speed of the
blinking cursor and the responsiveness to editing keypresses, e.g. with
fast keyboard auto-repeat settings. They probably wanted to be in a
fixed mode so the timing would be consistent, and it makes more sense to
force fast mode so that everything will go a little quicker.

> > Mega II isn't involved in DMA to fast banks (it has no knowledge of
> > memory outside its own two banks).
> 
> Mega II is connected to the expansion slots. Even if DMA is done to
> fast banks, it's still at 1 MHz.
> There should be handshake between Mega II and FPI, but I need some
> time to investigate.
> 
> > The FPI is in charge of all memory accesses (both CPU and DMA), and only
> > hands them over to the Mega II when addressing banks $E0 and $E1
> > (possibly via shadowing). If the IIgs is runing in fast mode, it
> > requires a sychronization between the 2.8 MHz cycle an the 1 MHz cycle.
> >
> > For a DMA cycle to fast memory, the FPI gets the bank from its DMA bank
> > register, and handles the entire thing without touching the Mega II.
> 
> Umm, I think the Mega II signals to FPI (and then reaches CPU possibly
> by means of RDY) that there is a DMA and FPI allows or disallows
> depending on the bank register.
> But I'm shooting in the dark.

I'd need to dig out my IIgs hardware reference and have a closer look at
the schematics.

Certainly for a normal CPU access, the FPI is in charge.

DMA is more complicated due to being initiated by an I/O card in a
certain phase of the 1 MHz cycle, while the FPI and CPU might be off
doing something else out of sync at 2.8 MHz.

It may be necessary to abort a fast CPU cycle in order to get out of the
way of the DMA access.

-- 
David Empson
dempson@actrix.gen.nz