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Re: An FPGA card for Apple

alex.freed.007@gmail.com wrote:


Unfortunately the PLL needs a 10 MHz minimum input clock and only
7 MHz is available on the Apple bus. Using an external (to Apple)
clock
makes it less appealing to our sense of harmony :)


Cyclone 3 can take down to 5MHz! ;)


And you can always use Altium Designer as a vendor neutral tool.


[SHUDDER]

Regards,

--
|              Mark McDougall                | "Electrical Engineers do it
|  <http://members.iinet.net.au/~msmcdoug>   |   with less resistance!"