"John B. Matthews" <nospam@nospam.invalid> wrote in message nospam-1DEF0D.08155419092008@news.motzarella.org">news:nospam-1DEF0D.08155419092008@news.motzarella.org...
In article <bc6ac1d2-ca03-49ea-bb09-02fe018c2bdb@b38g2000prf.googlegroups.com>,David Wilson <mcs6502@gmail.com> wrote:On Sep 19, 6:39 am, "John B. Matthews" <nos...@nospam.invalid> wrote: > > > >> Translation: > > > >> LDA #$10 > > > >> STA $C08B ;ACIA_Control Register > > > >> LDA #$0B > > > >> STA $C0AA ;ACIA_Command Register > > > >> LDA $C0A8 ;ACIA_Data > > > >> RTS > Ah, I see. Then there's some kind of 32x external clock? > $0B (%00001011): 1 stop bit, 8 data bits, external clock, 3600 baud.The $10 stored in the control reg selects 1 stop, 8 bits, ext rx clk, XTL/16 bps where XTL = 1.8432 MHz so the baud rate is 115200 bps.Thanks, David. I had the command and control registers reversed when I tried to interpret the values.Also, my table was wrong. I had incorrectly indicated that clearing the low nibble of the control register specified an external clock, which is actually specified in bit four. I think I fixed it:<http://home.woh.rr.com/jbmatthews/ssc.html#tbl3>
"Bits 0-3 clear: 1,843,200 MHz / 16 = 115,200 baud" Getting there, the above should read: "Bits 0-3 clear: 1,843,200 Hz / 16 = 115,200 baud" ;-)
Bill Garber from GS-Electronics http://www.garberstreet.com"If you wish to forget anything on the spot, make a note that this thing is to be remembered." (Edgar Allen Poe)