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Re: 65816's



Michael J. Mahon wrote:
glen herrmannsfeldt wrote:
Steven Hirsch wrote:

(snip)

As other's have commented, it's probably hard to find fabs that maintain tooling for 0.8 micron. Also, a process shrink does not necessarily speed things up. I work in the business and have seen many cases where improvements in device switching speed are more than offset by increased wiring delays on the backend layers. As a matter of fact, for almost any technology produced in the last 10 years or so, wire delays generally predominate.


The change from 0.8u to 0.6u was a big one.  For 0.8u and above,
it works well to consider a wire as a wire with the same voltage
everywhere.   The delay is caused by the capacitance to ground.

For 0.6, the resistance increases by a factor of (0.8/0.6)
and the capacitance decreases by (0.6/0.8).  At this point,
it was necessary to consider the wires as resistors charging
distributed capacitors.  For long wires the added resistance is
not made up for by the decreased capacitance.  The timing now
depends more on the length than it did at 0.8u.

Yes, and it's faster to get across chip by going through a
couple of inverters than by using just a wire--quite a change
from adding up gate delays!  ;-)

High-end placement-aware synthesis tools (Cadence, Synopsys) stuff in buffers and inverters all over the place to close timing. The circuit you end up with can be quite different from what the original RTL description might suggest.

For a mere $50k per seat, per year, this can be yours at home <g>.

Steve