Re: 65816's

[glen herrmannsfeldt <gah@ugcs.caltech.edu>]

Steven Hirsch wrote:

(snip)

> High-end placement-aware synthesis tools (Cadence, Synopsys) stuff in 
> buffers and inverters all over the place to close timing.  The circuit 
> you end up with can be quite different from what the original RTL 
> description might suggest.

Before 0.6u many times a new chip was made by just shrinking the mask,
without any other changes.  That might still have been done at 0.6u,
but more likely the additional buffers would need to be added.

> For a mere $50k per seat, per year, this can be yours at home <g>.

Another reason FPGAs are getting more popular for new designs.
The other reason is the cost of masks approaching $1M.

-- glen