Re: 65C02 emulation

[bieling@terra.es]

Charlie Springer ha escrito:

> On Mon, 25 Dec 2006 15:24:23 -0800, bieling@terra.es wrote
> (in article <1167089063.194461.99810@h40g2000cwb.googlegroups.com>):
>
> > I mean, although this board is not intended to be used for development,
> > it looks like it's being used for.
> > You may find it useful for your ARM-65c02 emulation experiments.
>
> Jorge, thanks for the info. There are several small boards with ARM9 on them
> now. So, as soon as I get an ARM7 working I can jump from 60 MHz to 200 MHz
> for very little cost.

So, what development board are you using/considering to use  ?
What IDE ?

> Also, Atmel has announced an ARM7T chip with some FLASH and RAM for less than
> $3. I bet the parts cost for an emulation accelerator could be less than $10
> excluding the PCB (which changes so much with volume). Might as well add the
> CFcard capability and a few other goodies -- USB and Ethernet?
>
> I was talking to an old friend who is a designer at Apple and we were
> laughing about how we could use an ARM to "bit-bang" the Apple II bus. On a
> one MHz bus we can do 200 ARM instructions per phase II cycle. He once
> completely emulated the IWM in software and says the disk I/O and such "are
> trivial". I bet I could set an interrupt on the Apple clock and meet all the
> timing requirements for read/write using ARM I/O lines run by software.
>
> -- Charlie Springer

I see. There are 200 ARM(9) "steps" in every Apple II 1000ns bus cycle.
Between 60 and 80 for an ARM7. At first sight this gives you an
"accuracy" of between 5 and 17 ns ! (For what it may be worth, remember
that some Apple II cycles are longer than the rest)
But do you know if the peripheral bus in and ARM9 runs at the cpu core
speed ? I ask because even though that''s true for almost every ARM7 I
have checked (although it has to be configured so, usually it defaults
to a fraction of the speed of the ARM core), I'm not sure about ARM9's.
The idea itself is funny. But then the clocks should be well locked and
in phase. The difference in phase has to be accounted for (it worses
the "accuracy" figure). And the clock jitter of the ARM, if any (it
usually runs from a PLL). How many time have you got after the falling
edge of the 6502 bus clock in order to sample reads from the Apple II
MLB ?, I ask because there's the interrupt latency time. It does not
look like a problem for writes to the Apple II MLB. In the end, I bet
you'll prefer to use some glue logic (cpld) to ease the timing
requirements. Although if you definitinely *want to*, you probably can
go without it, at the cost of some ARM cpu bandwith. Probably you could
even choose to poll the Apple II bus... :-)

How's the project going ?

Happy Holidays,
Jorge Chamorro.