Re: PseudoDisk][ and IIGS

["RedskullDC" <RDC@oz.org>]

Hi Alex,

Is your circuit anywhere on the web? (Couldn't see it on your page).

Using 6522's on the Apple bus required lengthening the clock phases,
since the Apple generated signals weren't long enough as I recall.
http://rich12345.tripod.com/schematics/6522.html on Rich's page
will give you an idea what I mean. May be the problem?

Do you disable interrupts before a transfer? Does your card have
the daisy-chain set up on the int and dma lines? Can't say for sure
from the pics on your site.

Page 184 of the 2GS hardware manual gives more info on the timing.
Can be found here:
http://www.apple-iigs.info/doc/home.htm

Have you tried setting the "speed" register at $C036 to force low
speed during your accesses?

Bits 3,2,1,0 corresspond to slots 7,6,5,4 respectively.
If the bit in question is set to '1', the 2GS will look for "Disk][" type
accesses in the corressponding slot.
ie.
Set bit 0 to 1.
Access $C0F9  (motor on if you had a disk2 in slot#7)
GS is now running at 1.024MHz regardless.
Access $C0F8 (motor-off for slot#7)
GS is now running at it's previous speed.

Hope this helps.
Red
"Alex Freed" <alexf@mirrow.com> wrote in message 
L9adnfCfNOqFtuTYnZ2dnUVZ_rGdnZ2d@comcast.com">news:L9adnfCfNOqFtuTYnZ2dnUVZ_rGdnZ2d@comcast.com...
> One other person confirmed my observations regarding the IIGS.
> Bill Garber told me that he also noticed flaky behavior on a GS
> "getting much worse at high speed".
>
> To test the theory I had about putting the data on the bus too early
> I have wired one extra signal - Q3 - from the slot and modified the
> CPLD to use it. As a result the boot process became more reliable
> but the other problem remains - NIB images work fine but the
> ProDOS image does not. The message "Can't load PRODOS" is
> all I get.
>
> The logic analyzer shows that this happens as a result of a checksum
> error reading a block. Not the same block every time. So some byte
> gets corrupted in transit from the AVR to the IIGS bus. Furthermore
> plugging the logic analyzer itself  into a slot makes the problem worse.
> And this is a modern tool with rather low load capacitance. This also
> indicates a marginal timing on the bus. Yet I don't see anything wrong
> with a scope.
> The NIB images work because DOS re-reads blocks in case of errors.
> Apparently ProDOS doesn't always do it.
>
> If anyone has any information on IIGS slot timing, please let me know.
>
>
> -- 
> -Alex.
>
>