Re: Monitor Problems

["mdj" <mdj.mdj@gmail.com>]

Michael J. Mahon wrote:

> > One wonders when the 'wall' of CMOS switching speed will be reached and
> > we have to start exploring ECL designs again. Certainly that's been
> > said before, but there's something about the design that really appeals
> > to me.
>
> Most of the power that CMAS dissipates is "AC power" associated with
> switching (and the consequent charging/discharging of capacitance).
> The quiescent power for CMOS is quite low--unless the process is
> making very leaky transistors.
>
> So the only way to dissipate less power at high frequency is to 1)
> decrease resistance, 2) decrease capacitance, or (most popular) 3,
> decrease voltage swing.
>
> Efforts are proceeding on all fronts:  copper in place of aluminum to
> reduce resistance, low dielectric insulating layers to reduce
> capacitance, and lowering operating voltage.  Unfortunately, all three
> are becoming more difficult, so maximum clock frequencies are not rising
> like they used to, and Moore's "Law" isn't being enforced like it was.
> ;-)

Indeed. I was more musing that at some point it may be necessary to
move to emitter-coupled designs in order to increase the switching
speed of current processes further. Certainly in modern designs where
the number of transistors switching per clock  cycle is massive, there
might not be much difference in current dissipation.

Matt