Re: RFC : SOME IDEAS FOR THE APPLE II FPGA'ers

[bieling@terra.es (Jorge Chamorro Bieling)]

Michael J. Mahon <mjmahon@aol.com> wrote:

> Useless is OK with me (this is for fun, after all), but what is the
> metric for "warmer" and "colder"?

Cool: more 6502 MIPS on the first place.
The fastest instruction takes 2 memory bus cycles.
The slowest takes 8 memory bus cycles.
The memory bus runs at 1MHz.
So we are between 0.5 (1/2) and 0.125 (1/8) MIPS.

The memory bus cycles could be shortened to let's say, 33nS for example.
This equals a 30x (1000/33) speedup.
The memory bus widened to 4 bytes, so as to reduce que required memory
cycles per instruction. Let's say that instead of 2..8 cycles, we manage
to shorten this to 1..3. This may translate into an additional 2.5x
speedup.

Now, multiply both : 2.5 times 30 equals 75 times faster.
MIPS are now between 10 (30/3) and 30 (30/1).
That's cool.

Now go and buy an off-the-shelf 65c02@14Mhz.
Interface it properly to the Apple II, and you've got between 14/8 and
14/2 MIPS, between 1.75 and 7 MIPS.
That's not-so-cool. 
But it's ok too.

-- 
Jorge Chamorro Bieling