aiiadict@gmail.com wrote:
The 2e could easily be replicated in the FPGA entirely, but that would render all your peripheral cards useless,Make the FPGA pins the peripheral slot connector pins, and you only *have to* slow down the 6502 in FPGA when accessing the $C100-$C7FF areas of RAM..
Not so--RWTS runs in RAM and it must be run slow. This is why the Zip Chip (and others) start slow mode whenever a slow slot /DEVSEL address is referenced, and then maintain slow mode for a heuristically determined 50-or-so milliseconds after a slow slot /DEVSEL reference. -michael Music synthesis for 8-bit Apple II's! Home page: http://members.aol.com/MJMahon/ "The wastebasket is our most important design tool--and it is seriously underused."