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Re: 74xx symbols from Xilinx ISE?

Subject: Re: 74xx symbols from Xilinx ISE?
From: "logjam" <grant@cmosxray.com>
Date: 13 Feb 2006 17:34:10 -0800
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My schematic program has the option to generate a VHDL schematic
netlist.  How is this used to simulate my schematic?  Can this netlist
be used to design FPGA code based on my schematic made entirely out of
TTL logic?  Here is a sample from my LED display:

LIBRARY IEEE
USE IEEE.std_logic_1164.all

ENTITY RW IS PORT
(
); END RW;

ARCHITECTURE STRUCTURE OF RW IS

-- COMPONENTS

COMPONENT DEVICE__CAP_NP PORT
(
  \1\ : IN std_logic;
  \2\ : IN std_logic
); END COMPONENT;

COMPONENT CONNECTOR__HEADER_15X2 PORT
(
  \1\ : IN std_logic;
  \2\ : IN std_logic;
  \3\ : IN std_logic;
  \4\ : IN std_logic;
  \5\ : IN std_logic;
  \6\ : IN std_logic;
  \7\ : IN std_logic;
  \8\ : IN std_logic;
  \9\ : IN std_logic;
  \10\ : IN std_logic;
  \11\ : IN std_logic;
  \12\ : IN std_logic;
  \13\ : IN std_logic;
  \14\ : IN std_logic;
  \15\ : IN std_logic;
  \16\ : IN std_logic;
  \17\ : IN std_logic;
  \18\ : IN std_logic;
  \19\ : IN std_logic;
  \20\ : IN std_logic;
  \21\ : IN std_logic;
  \22\ : IN std_logic;
  \23\ : IN std_logic;
  \24\ : IN std_logic;
  \25\ : IN std_logic;
  \26\ : IN std_logic;
  \27\ : IN std_logic;
  \28\ : IN std_logic;
  \29\ : IN std_logic;
  \30\ : IN std_logic
); END COMPONENT;

COMPONENT CONNECTOR__HEADER_7 PORT
(
  \1\ : IN std_logic;
  \2\ : IN std_logic;
  \3\ : IN std_logic;
  \4\ : IN std_logic;
  \5\ : IN std_logic;
  \6\ : IN std_logic;
  \7\ : IN std_logic
); END COMPONENT;

COMPONENT CONNECTOR__HEADER_2 PORT
(
  \1\ : IN std_logic;
  \2\ : IN std_logic
); END COMPONENT;

COMPONENT TTL__74S133 PORT
(
  I0 : IN std_logic;
  I1 : IN std_logic;
  I2 : IN std_logic;
  I3 : IN std_logic;
  I4 : IN std_logic;
  I5 : IN std_logic;
  I6 : IN std_logic;
  GND : IN std_logic;
  O : OUT std_logic;
  I7 : IN std_logic;
  I8 : IN std_logic;
  I9 : IN std_logic;
  I10 : IN std_logic;
  I11 : IN std_logic;
  I12 : IN std_logic;
  VCC : IN std_logic
); END COMPONENT;

COMPONENT TTL__74LS04 PORT
(
  I_A : IN std_logic;
  O_A : OUT std_logic;
  I_B : IN std_logic;
  O_B : OUT std_logic;
  I_C : IN std_logic;
  O_C : OUT std_logic;
  GND : IN std_logic;
  O_D : OUT std_logic;
  I_D : IN std_logic;
  O_E : OUT std_logic;
  I_E : IN std_logic;
  O_F : OUT std_logic;
  I_F : IN std_logic;
  VCC : IN std_logic
); END COMPONENT;

COMPONENT TTL__74LS138 PORT
(
  A : IN std_logic;
  B : IN std_logic;
  C : IN std_logic;
  G2A : IN std_logic;
  G2B : IN std_logic;
  G1 : IN std_logic;
  Y7 : OUT std_logic;
  GND : IN std_logic;
  Y6 : OUT std_logic;
  Y5 : OUT std_logic;
  Y4 : OUT std_logic;
  Y3 : OUT std_logic;
  Y2 : OUT std_logic;
  Y1 : OUT std_logic;
  Y0 : OUT std_logic;
  VCC : IN std_logic
); END COMPONENT;

COMPONENT TTL__74LS244 PORT
(
  \1G\ : IN std_logic;
  \1A1\ : IN std_logic;
  \2Y4\ : INOUT std_logic;
  \1A2\ : IN std_logic;
  \2Y3\ : INOUT std_logic;
  \1A3\ : IN std_logic;
  \2Y2\ : INOUT std_logic;
  \1A4\ : IN std_logic;
  \2Y1\ : INOUT std_logic;
  GND : IN std_logic;
  \2A1\ : IN std_logic;
  \1Y4\ : INOUT std_logic;
  \2A2\ : IN std_logic;
  \1Y3\ : INOUT std_logic;
  \2A3\ : IN std_logic;
  \1Y2\ : INOUT std_logic;
  \2A4\ : IN std_logic;
  \1Y1\ : INOUT std_logic;
  \2G\ : IN std_logic;
  VCC : IN std_logic
); END COMPONENT;

COMPONENT TTL__74LS273 PORT
(
  CLR : IN std_logic;
  Q1 : OUT std_logic;
  D1 : IN std_logic;
  D2 : IN std_logic;
  Q2 : OUT std_logic;
  Q3 : OUT std_logic;
  D3 : IN std_logic;
  D4 : IN std_logic;
  Q4 : OUT std_logic;
  GND : IN std_logic;
  CLK : IN std_logic;
  Q5 : OUT std_logic;
  D5 : IN std_logic;
  D6 : IN std_logic;
  Q6 : OUT std_logic;
  Q7 : OUT std_logic;
  D7 : IN std_logic;
  D8 : IN std_logic;
  Q8 : OUT std_logic;
  VCC : IN std_logic
); END COMPONENT;

COMPONENT DEVICE__NPN_BEC PORT
(
  BASE : IN std_logic;
  EMITTER : IN std_logic;
  COLLECTOR : IN std_logic
); END COMPONENT;

COMPONENT DEVICE__R PORT
(
  \1\ : IN std_logic;
  \2\ : IN std_logic
); END COMPONENT;

-- SIGNALS

SIGNAL A0_1 : std_logic;
SIGNAL A1_1 : std_logic;
SIGNAL A2_1 : std_logic;
SIGNAL A3_1 : std_logic;
SIGNAL A4_1 : std_logic;
SIGNAL A5_1 : std_logic;
SIGNAL A6_1 : std_logic;
SIGNAL A7_1 : std_logic;
SIGNAL A8_1 : std_logic;
SIGNAL A9_1 : std_logic;
SIGNAL \A\\3\\_1\ : std_logic;
SIGNAL \A\\4\\_1\ : std_logic;
SIGNAL \A\\5\\_1\ : std_logic;
SIGNAL \A\\6\\_1\ : std_logic;
SIGNAL \A\\7\\_1\ : std_logic;
SIGNAL \A\\8\\_1\ : std_logic;
SIGNAL \A\\9\\_1\ : std_logic;
SIGNAL \C\\L\\E\\A\\R\\_1\ : std_logic;
SIGNAL \C\\L\\O\\C\\K\\_1\ : std_logic;
SIGNAL CLEAR_1 : std_logic;
SIGNAL D0_1 : std_logic;
SIGNAL D1_1 : std_logic;
SIGNAL D2_1 : std_logic;
SIGNAL D3_1 : std_logic;
SIGNAL D4_1 : std_logic;
SIGNAL D5_1 : std_logic;
SIGNAL D6_1 : std_logic;
SIGNAL D7_1 : std_logic;
SIGNAL DI0_1 : std_logic;
SIGNAL DI1_1 : std_logic;
SIGNAL DI2_1 : std_logic;
SIGNAL DI3_1 : std_logic;
SIGNAL DI4_1 : std_logic;
SIGNAL DI5_1 : std_logic;
SIGNAL DI6_1 : std_logic;
SIGNAL DI7_1 : std_logic;
SIGNAL GND : std_logic;
SIGNAL \S\\E\\L\\_1\ : std_logic;
SIGNAL \S\\E\\L\\_\\A\\_1\ : std_logic;
SIGNAL \S\\E\\L\\_\\B\\_1\ : std_logic;
SIGNAL \S\\E\\L\\_\\C\\_1\ : std_logic;
SIGNAL \S\\E\\L\\_\\D\\_1\ : std_logic;
SIGNAL \S\\E\\L\\_\\E\\_1\ : std_logic;
SIGNAL \S\\E\\L\\_\\F\\_1\ : std_logic;
SIGNAL \S\\E\\L\\_\\G\\_1\ : std_logic;
SIGNAL \S\\E\\L\\_\\H\\_1\ : std_logic;
SIGNAL VCC : std_logic;
SIGNAL NET1_1 : std_logic;
SIGNAL NET2_1 : std_logic;
SIGNAL NET3_1 : std_logic;
SIGNAL NET4_1 : std_logic;
SIGNAL NET5_1 : std_logic;
SIGNAL NET6_1 : std_logic;
SIGNAL NET7_1 : std_logic;

-- GATE INSTANCES

BEGIN

C1 : DEVICE__CAP_NP PORT MAP
(
  \1\ => VCC,
  \2\ => GND
);

C2 : DEVICE__CAP_NP PORT MAP
(
  \1\ => VCC,
  \2\ => GND
);

C3 : DEVICE__CAP_NP PORT MAP
(
  \1\ => VCC,
  \2\ => GND
);

C4 : DEVICE__CAP_NP PORT MAP
(
  \1\ => VCC,
  \2\ => GND
);

C5 : DEVICE__CAP_NP PORT MAP
(
  \1\ => VCC,
  \2\ => GND
);

C6 : DEVICE__CAP_NP PORT MAP
(
  \1\ => VCC,
  \2\ => GND
);

C7 : DEVICE__CAP_NP PORT MAP
(
  \1\ => VCC,
  \2\ => GND
);

C8 : DEVICE__CAP_NP PORT MAP
(
  \1\ => VCC,
  \2\ => GND
);

C9 : DEVICE__CAP_NP PORT MAP
(
  \1\ => VCC,
  \2\ => GND
);

C10 : DEVICE__CAP_NP PORT MAP
(
  \1\ => VCC,
  \2\ => GND
);

C11 : DEVICE__CAP_NP PORT MAP
(
  \1\ => VCC,
  \2\ => GND
);

C12 : DEVICE__CAP_NP PORT MAP
(
  \1\ => VCC,
  \2\ => GND
);

J1 : CONNECTOR__HEADER_15X2 PORT MAP
(
  \1\ => A0_1,
  \2\ => A1_1,
  \3\ => A2_1,
  \4\ => A3_1,
  \5\ => A4_1,
  \6\ => A5_1,
  \7\ => A6_1,
  \8\ => A7_1,
  \9\ => A8_1,
  \10\ => A9_1,
  \11\ => DI0_1,
  \12\ => DI1_1,
  \13\ => DI2_1,
  \14\ => DI3_1,
  \15\ => DI4_1,
  \16\ => DI5_1,
  \17\ => DI6_1,
  \18\ => DI7_1,
  \19\ => CLEAR_1,
  \20\ => \C\\L\\O\\C\\K\\_1\,
  \21\ => GND,
  \22\ => GND,
  \23\ => GND,
  \24\ => GND,
  \25\ => GND,
  \26\ => VCC,
  \27\ => VCC,
  \28\ => VCC,
  \29\ => VCC,
  \30\ => VCC
);

J2 : CONNECTOR__HEADER_7 PORT MAP
(
  \1\ => A3_1,
  \2\ => A4_1,
  \3\ => A5_1,
  \4\ => A6_1,
  \5\ => A7_1,
  \6\ => A8_1,
  \7\ => A9_1
);

J3 : CONNECTOR__HEADER_7 PORT MAP
(
  \1\ => \A\\3\\_1\,
  \2\ => \A\\4\\_1\,
  \3\ => \A\\5\\_1\,
  \4\ => \A\\6\\_1\,
  \5\ => \A\\7\\_1\,
  \6\ => \A\\8\\_1\,
  \7\ => \A\\9\\_1\
);

J4 : CONNECTOR__HEADER_7 PORT MAP
(
  \1\ => NET7_1,
  \2\ => NET6_1,
  \3\ => NET5_1,
  \4\ => NET4_1,
  \5\ => NET3_1,
  \6\ => NET2_1,
  \7\ => NET1_1
);

J5 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J6 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J7 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J8 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J9 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J10 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J11 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J12 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J13 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J14 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J15 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J16 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J17 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J18 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J19 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J20 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J21 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J22 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J23 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J24 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J25 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J26 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J27 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J28 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J29 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J30 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J31 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J32 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J33 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J34 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J35 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J36 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J37 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J38 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J39 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J40 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J41 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J42 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J43 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J44 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J45 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J46 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J47 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J48 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J49 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J50 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J51 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J52 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J53 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J54 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J55 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J56 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J57 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J58 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J59 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J60 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J61 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J62 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J63 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J64 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J65 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J66 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J67 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

J68 : CONNECTOR__HEADER_2 PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

U1 : TTL__74S133 PORT MAP
(
  I0 => NET7_1,
  I1 => NET6_1,
  I2 => NET5_1,
  I3 => NET4_1,
  I4 => NET3_1,
  I5 => NET2_1,
  I6 => NET1_1,
  GND => GND,
  O => \S\\E\\L\\_1\,
  I7 => VCC,
  I8 => VCC,
  I9 => VCC,
  I10 => VCC,
  I11 => VCC,
  I12 => VCC,
  VCC => VCC
);

U2 : TTL__74LS04 PORT MAP
(
  I_A => A3_1,
  O_A => \A\\3\\_1\,
  I_B => A4_1,
  O_B => \A\\4\\_1\,
  I_C => A5_1,
  O_C => \A\\5\\_1\,
  GND => GND,
  O_D => \A\\6\\_1\,
  I_D => A6_1,
  O_E => \A\\7\\_1\,
  I_E => A7_1,
  O_F => \A\\8\\_1\,
  I_F => A8_1,
  VCC => VCC
);

U3 : TTL__74LS04 PORT MAP
(
  I_A => A9_1,
  O_A => \A\\9\\_1\,
  I_B => CLEAR_1,
  O_B => \C\\L\\E\\A\\R\\_1\,
  I_C => OPEN,
  O_C => OPEN,
  GND => GND,
  O_D => OPEN,
  I_D => OPEN,
  O_E => OPEN,
  I_E => OPEN,
  O_F => OPEN,
  I_F => OPEN,
  VCC => VCC
);

U4 : TTL__74LS138 PORT MAP
(
  A => A0_1,
  B => A1_1,
  C => A2_1,
  G2A => \S\\E\\L\\_1\,
  G2B => \C\\L\\O\\C\\K\\_1\,
  G1 => VCC,
  Y7 => \S\\E\\L\\_\\H\\_1\,
  GND => GND,
  Y6 => \S\\E\\L\\_\\G\\_1\,
  Y5 => \S\\E\\L\\_\\F\\_1\,
  Y4 => \S\\E\\L\\_\\E\\_1\,
  Y3 => \S\\E\\L\\_\\D\\_1\,
  Y2 => \S\\E\\L\\_\\C\\_1\,
  Y1 => \S\\E\\L\\_\\B\\_1\,
  Y0 => \S\\E\\L\\_\\A\\_1\,
  VCC => VCC
);

U5 : TTL__74LS244 PORT MAP
(
  \1G\ => GND,
  \1A1\ => DI0_1,
  \2Y4\ => D7_1,
  \1A2\ => DI1_1,
  \2Y3\ => D6_1,
  \1A3\ => DI2_1,
  \2Y2\ => D5_1,
  \1A4\ => DI3_1,
  \2Y1\ => D4_1,
  GND => GND,
  \2A1\ => DI4_1,
  \1Y4\ => D3_1,
  \2A2\ => DI5_1,
  \1Y3\ => D2_1,
  \2A3\ => DI6_1,
  \1Y2\ => D1_1,
  \2A4\ => DI7_1,
  \1Y1\ => D0_1,
  \2G\ => GND,
  VCC => VCC
);

U6 : TTL__74LS273 PORT MAP
(
  CLR => \C\\L\\E\\A\\R\\_1\,
  Q1 => OPEN,
  D1 => D0_1,
  D2 => D1_1,
  Q2 => OPEN,
  Q3 => OPEN,
  D3 => D2_1,
  D4 => D3_1,
  Q4 => OPEN,
  GND => GND,
  CLK => \S\\E\\L\\_\\A\\_1\,
  Q5 => OPEN,
  D5 => D4_1,
  D6 => D5_1,
  Q6 => OPEN,
  Q7 => OPEN,
  D7 => D6_1,
  D8 => D7_1,
  Q8 => OPEN,
  VCC => VCC
);

U7 : TTL__74LS273 PORT MAP
(
  CLR => \C\\L\\E\\A\\R\\_1\,
  Q1 => OPEN,
  D1 => D0_1,
  D2 => D1_1,
  Q2 => OPEN,
  Q3 => OPEN,
  D3 => D2_1,
  D4 => D3_1,
  Q4 => OPEN,
  GND => GND,
  CLK => \S\\E\\L\\_\\C\\_1\,
  Q5 => OPEN,
  D5 => D4_1,
  D6 => D5_1,
  Q6 => OPEN,
  Q7 => OPEN,
  D7 => D6_1,
  D8 => D7_1,
  Q8 => OPEN,
  VCC => VCC
);

U8 : TTL__74LS273 PORT MAP
(
  CLR => \C\\L\\E\\A\\R\\_1\,
  Q1 => OPEN,
  D1 => D0_1,
  D2 => D1_1,
  Q2 => OPEN,
  Q3 => OPEN,
  D3 => D2_1,
  D4 => D3_1,
  Q4 => OPEN,
  GND => GND,
  CLK => \S\\E\\L\\_\\E\\_1\,
  Q5 => OPEN,
  D5 => D4_1,
  D6 => D5_1,
  Q6 => OPEN,
  Q7 => OPEN,
  D7 => D6_1,
  D8 => D7_1,
  Q8 => OPEN,
  VCC => VCC
);

U9 : TTL__74LS273 PORT MAP
(
  CLR => \C\\L\\E\\A\\R\\_1\,
  Q1 => OPEN,
  D1 => D0_1,
  D2 => D1_1,
  Q2 => OPEN,
  Q3 => OPEN,
  D3 => D2_1,
  D4 => D3_1,
  Q4 => OPEN,
  GND => GND,
  CLK => \S\\E\\L\\_\\G\\_1\,
  Q5 => OPEN,
  D5 => D4_1,
  D6 => D5_1,
  Q6 => OPEN,
  Q7 => OPEN,
  D7 => D6_1,
  D8 => D7_1,
  Q8 => OPEN,
  VCC => VCC
);

U10 : TTL__74LS273 PORT MAP
(
  CLR => \C\\L\\E\\A\\R\\_1\,
  Q1 => OPEN,
  D1 => D0_1,
  D2 => D1_1,
  Q2 => OPEN,
  Q3 => OPEN,
  D3 => D2_1,
  D4 => D3_1,
  Q4 => OPEN,
  GND => GND,
  CLK => \S\\E\\L\\_\\H\\_1\,
  Q5 => OPEN,
  D5 => D4_1,
  D6 => D5_1,
  Q6 => OPEN,
  Q7 => OPEN,
  D7 => D6_1,
  D8 => D7_1,
  Q8 => OPEN,
  VCC => VCC
);

U11 : TTL__74LS273 PORT MAP
(
  CLR => \C\\L\\E\\A\\R\\_1\,
  Q1 => OPEN,
  D1 => D0_1,
  D2 => D1_1,
  Q2 => OPEN,
  Q3 => OPEN,
  D3 => D2_1,
  D4 => D3_1,
  Q4 => OPEN,
  GND => GND,
  CLK => \S\\E\\L\\_\\F\\_1\,
  Q5 => OPEN,
  D5 => D4_1,
  D6 => D5_1,
  Q6 => OPEN,
  Q7 => OPEN,
  D7 => D6_1,
  D8 => D7_1,
  Q8 => OPEN,
  VCC => VCC
);

U12 : TTL__74LS273 PORT MAP
(
  CLR => \C\\L\\E\\A\\R\\_1\,
  Q1 => OPEN,
  D1 => D0_1,
  D2 => D1_1,
  Q2 => OPEN,
  Q3 => OPEN,
  D3 => D2_1,
  D4 => D3_1,
  Q4 => OPEN,
  GND => GND,
  CLK => \S\\E\\L\\_\\D\\_1\,
  Q5 => OPEN,
  D5 => D4_1,
  D6 => D5_1,
  Q6 => OPEN,
  Q7 => OPEN,
  D7 => D6_1,
  D8 => D7_1,
  Q8 => OPEN,
  VCC => VCC
);

U13 : TTL__74LS273 PORT MAP
(
  CLR => \C\\L\\E\\A\\R\\_1\,
  Q1 => OPEN,
  D1 => D0_1,
  D2 => D1_1,
  Q2 => OPEN,
  Q3 => OPEN,
  D3 => D2_1,
  D4 => D3_1,
  Q4 => OPEN,
  GND => GND,
  CLK => \S\\E\\L\\_\\B\\_1\,
  Q5 => OPEN,
  D5 => D4_1,
  D6 => D5_1,
  Q6 => OPEN,
  Q7 => OPEN,
  D7 => D6_1,
  D8 => D7_1,
  Q8 => OPEN,
  VCC => VCC
);

Q1 : DEVICE__NPN_BEC PORT MAP
(
  BASE => OPEN,
  EMITTER => OPEN,
  COLLECTOR => OPEN
);

Q2 : DEVICE__NPN_BEC PORT MAP
(
  BASE => OPEN,
  EMITTER => OPEN,
  COLLECTOR => OPEN
);

Q3 : DEVICE__NPN_BEC PORT MAP
(
  BASE => OPEN,
  EMITTER => OPEN,
  COLLECTOR => OPEN
);

Q4 : DEVICE__NPN_BEC PORT MAP
(
  BASE => OPEN,
  EMITTER => OPEN,
  COLLECTOR => OPEN
);

Q5 : DEVICE__NPN_BEC PORT MAP
(
  BASE => OPEN,
  EMITTER => OPEN,
  COLLECTOR => OPEN
);

Q6 : DEVICE__NPN_BEC PORT MAP
(
  BASE => OPEN,
  EMITTER => OPEN,
  COLLECTOR => OPEN
);

Q7 : DEVICE__NPN_BEC PORT MAP
(
  BASE => OPEN,
  EMITTER => OPEN,
  COLLECTOR => OPEN
);

Q8 : DEVICE__NPN_BEC PORT MAP
(
  BASE => OPEN,
  EMITTER => OPEN,
  COLLECTOR => OPEN
);

R1 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R2 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R3 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R4 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R5 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R6 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R7 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R8 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R9 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R10 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R11 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R12 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R13 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R14 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R15 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R16 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R17 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R18 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R19 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R20 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R21 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R22 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R23 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R24 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R25 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R26 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R27 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R28 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R29 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R30 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R31 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R32 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R33 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R34 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R35 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R36 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R37 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R38 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R39 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R40 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R41 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R42 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R43 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R44 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R45 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R46 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R47 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R48 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R49 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R50 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R51 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R52 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R53 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R54 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R55 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R56 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R57 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R58 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R59 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R60 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R61 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R62 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R63 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

R64 : DEVICE__R PORT MAP
(
  \1\ => OPEN,
  \2\ => OPEN
);

END STRUCTURE;
References:
- Re: 74xx symbols from Xilinx ISE?
  - From: "Michael J. Mahon" <mjmahon@aol.com>
- Re: 74xx symbols from Xilinx ISE?
  - From: aiiadict@gmail.com
- Re: 74xx symbols from Xilinx ISE?
  - From: "PZ" <skierpaul@yahoo.com>
- Re: 74xx symbols from Xilinx ISE?
  - From: aiiadict@gmail.com
- Re: 74xx symbols from Xilinx ISE?
  - From: "PZ" <skierpaul@yahoo.com>
- Re: 74xx symbols from Xilinx ISE?
  - From: ziggy <ziggy@fakedaddress.com>
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