Re: TransWarp IIgs GAL's - Upgrade now possible

[Eric Smith <eric@brouhaha.com>]

Henry wrote:
> Cloning the TransWarp IIgs but in to a new FPGA would be the path we would 
> take.  I may be wrong, but as stated earlier the "configuration code" for 
> the XC2064 on the TransWarp IIgs is stored in ROM?

Yes.

> So, again I haven't even 
> started any research on this, I would assume that if the code is readable 
> then converting it in to something logical (i.e. - HDL or schematic)
> should just be a matter of time.

The FPGA configuration bitstream format is not documented anywhere,
beyond that it has a header, a certain number of frames, and a trailer.
The content of a frame is not documented.

For an XC2064, it consists of 12,038 bits (just under 1505 bytes),
broken down as 160 frames of 71 bits (+ 4 bits framing overhead), 
and 38 bits of header/trailer overhead.

Bits in the frames configure the lookup tables, flip-flop, and
mulitplexer configuration in the 64 CLBs (Configurable Logic Blocks)
and the 58 IOBs (I/O Blocks), and all of the routing matrix
interconnections.

It's a significant challenge to convert it back to logic equations.  It
is probably easier to treat it as a black box, attach a logic analyzer
to the pins, capture traces of the the TWGS in operation, and deduce
what's going on inside the FPGA.

Having a schematic of the board together with the logic equations of
the GALs would help very much in figuring out what functions the
FPGA performs.

Eric