Michael J. Mahon wrote:
So the engineering interface to FPGAs is solely their design tools?
Correct.
That's quite remarkable--like not documenting the object code of a
processor but only providing a C compiler!
That's been done as well. For instance, the Echelon "Neuron" processor,
which at one time was manufactured and sold by Motorola and Toshiba.
I would have expected the low-level interface to be documented so that
third parties could produce design tools.
There are routinely flame wars about this over in comp.arch.fpga, but
the short and (not so) sweet summary is, "ain't gonna happen". Part of
the rationale that the FPGA vendors give for this policy is that their
customers WANT it to be difficult if not impossible to reverse engineer
a netlist or RTL from a bitstream.
Because the newer parts have embedded memory arrays ("block RAM"), they
document just enough of the bitstream to allow you to tweak the contents
of that memory using your own tools. Everything else about the
bitstream is opaque.
The current Xilinx tools ("Foundation ISE") allow you to load your
compiled (synthesized, mapped, placed, and routed) into an "FPGA
Editor", which will show you the details of the configuration of each
logic cell, I/O cell, the routing matrix, etc. However, it will not do
this for a final bitstream that you can read from a device, only for an
intermediate file, and they don't provide any tool that can transform
the final bitstream back into the intermediate format.
However, the XC2000 family was the very first family of FPGAs, and
has not been supported by any Xilinx software in many years. I think
it was only supported in their "XACT" software, and not in any version
of "Foundation" or "Alliance".