mspangler wrote:
OK, I'm baffled by this whole thread. How can a collection of NAND gates with blow-upable inputs act as a general purpose CPU? As a logic device replacer (MMU/IOU/74ls154 ect) it makes sense. But given you don't know what instructions are coming in what sequence, and there is microcode in the CPU that has to execute in a strict time sequence, I'm baffled. Is there is nice simple link that explains once over lightly how this works? confusedly yours;
The simple answer is that FPGAs have a _lot_ of gates (think hundreds of thousands), already arranged in useful chunks to build almost any digital device. An Apple II is a piece of cake relative to what can be implemented on even a medium- sized FPGA. Of course, external SRAM helps conserve FPGA cells. ;-) Here is a link to Xilinx' Programmable Logic Handbook: http://www.xilinx.com/publications/products/cpld/logic_handbook.pdf It addresses both the background and the specifics of FPGAs.
Michael J. Mahon wrote:I expect that the 6502 implementation on the FPGA uses a very minor part of the chips resources. There is no reason to use a slow, big, expensive, separate chip to do what can easily fit in a corner of an FPGA.
-michael 8-voice music synthesizer using NadaNet networking! Home page: http://members.aol.com/MJMahon/